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MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 3874 group is the 8-bit microcomputer based on the 740 family core technology. The 3874 group includes data link layer communication control circuit, A-D converters, D-A converter, automatic data transfer serial I/O, UART, and watchdog timer etc. The various microcomputers in the 3874 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3874 group, refer to the section on group expansion.
FEATURES
qBasic machine-language instructions ...................................... 71 qMinimum instruction execution time ................................. 0.32 s (at 6.4 MHz oscillation frequency, in double-speed mode) qMemory size ROM ............................................................... 16 K to 60 K bytes RAM ............................................................... 1024 to 2048 bytes qProgrammable input/output ports ............................................ 72 qInput port .................................................................................... 1 qInterrupts ................................................. 27 sources, 16 vectors (Interrupt source discrimination register exists, included key input interrupt) qTimer 1, timer 2, timer 3 ................................................. 8-bit ! 3 qTimer X, timer Y............................................................ 16-bit ! 2
qSerial I/O1 .................... 8-bit ! 1(UART or Clock-synchronized) qSerial I/O2 ................................... 8-bit ! 1(Clock-synchronized) qSerial I/O3 ...................................................................... 8-bit ! 1 (Clock-synchronized automatic data transfer/arbitrary bit transfer function available) qA-D converter ................................................. 8-bit ! 8 channels qD-A converter ................................................... 8-bit ! 1 channel qData link layer communication control circuit ............................ 1 qClock generating circuit ..................................... Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) qWatchdog timer ............................................................ 20-bit ! 1 qPower source voltage ................................................ 3.0 to 5.5 V qPower dissipation In double-speed mode ...................................................... 90 mW In high-speed mode .......................................................... 60 mW (at 32 kHz oscillation frequency, at 5 V power source voltage) In low-speed mode .......................................................... 180 W (at 32 kHz oscillation frequency, at 3 V power source voltage) qOperating temperature range .................................... -40 to 85C (Extended operating temperature version and automotive version)
APPLICATION
Automotive comfort control for audio system, air conditioning etc., automotive body electronics control, household appliances, and other consumer applications, etc.
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION PIN CONFIGURATION (TOP VIEW)
58
53
50 49 48
60
55
46
57
52
59
54
47
45
43
42 41
56
51
44
P32 P33 P34 P35 P36 P37 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15
P31 P30 P87/SSTB3 P86/SBUSY3 P85/SRDY3 P84/SCLK3 P83/SIN3 P82/SOUT3 P81 P80/DA VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8
40 39 38 37 36 35 34 33 32 31
M38747MCT-XXXGP
30 29 28 27 26 25 24 23 22 21
P16 P17 P20/KW0 P21/KW1 P22/KW2 P23/KW3 P24/KW4 P25/KW5 P26/KW6 P27/KW7 VSS XOUT XIN P40/XCOUT P41/XCIN RESET P97/INT0 P42/INT1 P43/INT2 P44/RXD
Fig. 1 M38747MCT-XXXGP pin configuration
2
P60/AN0 P77/ADT P76/BUSIN P75/BUSOUT P74 P73 P72/SCLK2 P71/SOUT2 P70/SIN2 P57/RTP1 P56/RTP0 P55/CNTR1 P54/CNTR0 P53/INT5 P52/INT4 P51/INT3 P50/TOUT P47/SRDY1 P46/SCLK1 P45/TXD
Package type : 80P6S-A
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
55
43
54
42
53
64
52
63
51
62
50
61
49
60
48
59
47
58
46
57
45
P87/SSTB3 P86/SBUSY3 P85/SRDY3 P84/SCLK3 P83/SIN3 P82/SOUT3 P81 P80/DA VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3
56
44
41
P30 P31 P32 P33 P34 P35 P36 P37 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
P20/KW0 P21/KW1 P22/KW2 P23/KW3 P24/KW4 P25/KW5 P26/KW6 P27/KW7 VSS XOUT XIN P40/XCOUT P41/XCIN RESET P97/INT0 P42/INT1
10
22
11
23
12
13
14
15
16
17
18
19
20
P72/SCLK2 P71/SOUT2 P70/SIN2 P57/RTP1 P56/RTP0 P55/CNTR1 P54/CNTR0 P53/INT5 P52/INT4 P51/INT3 P50/TOUT P47/SRDY1
P46/SCLK1 P45/TxD
21
P62/AN2 P61/AN1 P60/AN0 P77/ADT
Fig. 2 M38749EFFS pin configuration
P76/BUSIN P75/BUSOUT P74 P73
Package type : 80D0
P44/RxD P43/INT2
24
1
2
3
4
5
6
7
8
9
3
FUNCTIONAL BLOCK
4
Reset input RESET VSS
30 25 71
FUNCTIONAL BLOCK DIAGRAM (Package : 80P6S-A)
Main-clock input XIN (5V) VCC (0V)
Main-clock output X OUT
Fig. 3 Functional block diagram
Data bus Watchdog timer CPU Data link layer communication control circuit A ROM X Y S PCH PCL PS
BUSIN,BUSOUT RTP1,RTP0 CNTR1,CNTR0 TOUT Reset
28
29
Clock generating circuit
X COUT XCIN Sub-clock Sub-clock input output
Serial I/O3 automatic transfer RAM
Serial I/O3 automatic transfer controller
RAM
Timer X(16) Timer Y(16) Timer 1(8) Timer 2(8) Timer 3(8)
Local data bus
Reset
D-A converter (8) A-D converter (8) Serial I/O1(8)
Serial I/O2(8)
ADT INT2,INT1 INT5,INT4, INT3 XCOUT XCIN
Key-on wake-up
INT0 P9(1)
P8(8) P6(8) P5(8)
P7(8)
P4(8)
P3(8)
P2(8)
P1(8)
P0(8)
24
63 64 65 66 67 68 69 70 8 72 73 74 75 76 77 78 79 80 1 9
2
3
4
5
6
7
10 11 12 13 14 15 16 17
18 19 20 21 22 23 26 27
55 56 57 58 59 60 61 62
31 32 33 34 35 36 37 38
39 40 41 42 43 44 45 46
47 48 49 50 51 52 53 54
I/O port P9 I/O port P6 VREF AVSS I/O port P5 I/O port P4 I/O port P3 I/O port P2 I/O port P1 I/O port P0
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O port P8
I/O port P7
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description (1) Pin VCC, VSS VREF AVSS RESET XIN Name Power source input Reference voltage input Analog power source input Reset input Clock input Functions *Apply voltage of 3.0 V - 5.5 V to Vcc, and 0 V to Vss. *Reference voltage input pin for A-D and D-A conver ters. *Analog power source input pin for A-D and D-A converters. *Connect to VSS. *Reset input pin for active "L." *Input and output pins for the clock generating circuit. *Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. *When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. *Feedback resistor is built in between XIN pin and XOUT pin. *8-bit CMOS I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level. *CMOS 3-state output structure. *8-bit I/O port with the same function as port P0. *CMOS compatible input level. *CMOS 3-state output structure. *Sub-clock generating circuit I/O pins connect a resonator. (This circuit cannot be operated by an external clock.) *Interrupt input pins *Serial I/O1 function pins
Function except a port function
XOUT P00-P07 P10-P17 P20-P27 P30-P37 P40/XCOUT, P41/XCIN
Clock output I/O port P0 I/O port P1 I/O port P2 I/O port P3
P42/INT1, I/O port P4 P43/INT2 P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 P50/TOUT P51/INT3- P53/INT5 P54/CNTR0, I/O port P5 P55/CNTR1 P56/RTP0, P57/RTP1
*8-bit I/O port with the same function as port P0. *CMOS compatible input level. *CMOS 3-state output structure.
*Timer 2 output pin *Interrupt input pins *Timer X, timer Y function pins *Real time port function pins
5
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2 Pin description (2) Pin Name Functions Function except a port function *8-bit I/O port with the same function as port P0. P60/AN0- P67/AN7 P70/SIN2, P71/SOUT2, P72/SCLK2 P73, P74 P75/BUSOUT, P76/BUSIN P77/ADT P80/DA P81 P82/SOUT3, P83/SIN3, P84/SCLK3, P85/SRDY3 P86/SBUSY3, P87/SSTB3 P97/INT0 I/O port P7 *Data link layer communication control pins *A-D trigger input pin *D-A converter output pin *Serial I/O3 function pins I/O port P8 I/O port P6 *CMOS compatible input level. *CMOS 3-state output structure. *8-bit I/O port with the same function as port P0. *CMOS compatible input level. *CMOS 3-state output structure. *A-D converter input pins
*Serial I/O2 function pins
*8-bit I/O port with the same function as port P0.
Input port P9
*1-bit input port. *CMOS compatible input level.
*Interrupt input pin
6
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M3874
7
M
C T-
XXX
GP
Package type GP : 80P6S-A FS : 80D0
ROM number Omitted in some types. D- : Extended operating temperature version F- : Extended operating speed version of "D-" T- : Automotive version
ROM/PROM size 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C: 49152 bytes D: 53248 bytes E : 57344 bytes F : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used.
Memory type M : Mask ROM version E : EPROM or One Time PROM version
RAM size 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes
Fig. 4 Part numbering
7
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3874 group main clock input oscillation frequency in double-speed mode
* EPROM or One time PROM version
* Mask ROM version
Main clock input oscillation frequency f(X IN) (MHz)
6.4 MHz 5 MHz
Main clock input oscillation frequency f(X IN) (MHz)
6.4 MHz
4.0 V 4.5 V
5.5 V
4.0 V
5.5 V
Power source voltage V CC (V)
Power source voltage V CC (V)
In low-speed mode, middle-speed mode, and high-speed mode, characteristic of main clock input oscillation frequency guarantee limit is not different.
Fig. 5 Main clock input oscillation frequency in double-speed mode
8
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION (Extended operating temperature version)
The 3874 group (extended operating temperature version) is designed for automotive comfort and amusement control such as audio, air-conditioner etc., household appliances, and other consumer applications. Mitsubishi plans to expand the 3874 group (extended operating temperature version) as follows:
Memory Type
Support for mask ROM, One Time PROM, and EPROM versions
Memory Size
ROM/PROM size ............................................... 48 K to 60 K bytes RAM size .......................................................... 1024 to 2048 bytes
Packages
80P6S-A .................................. 0.65 mm-pitch plastic molded QFP 80D0 ....................... 0.8 mm-pitch ceramic LCC (EPROM version)
Memory Expansion Plan of 3874 group (Extended operating temperature version)
ROM size (bytes) 60K 56K 52K 48K 44K 40K 36K 32K 28K 24K 20K 16K 1024 RAM size (byte) 1536 2048 Mass product M38747MCF Mass product M38749MFF/EFD
Products under development or planning : the development schedule and specification may be revised without notice. Planning products may be stopped during the development.
Fig. 6 Memory expansion plan (Extended operating temperature version) Currently planning products are listed below. Table 3 Support products Product name M38749EFDGP M38749EFFS M38749MFF M38747MCF 49152 (49022) 80P6S-A 1024 Mask ROM version 61440 (61310) 2048 (P) ROM size (bytes) ROM size for User in ( ) RAM size (bytes) Package 80P6S-A 80D0 Remarks One Time PROM version (blank) EPROM version (for software development, operating temperature = -20 to 85C) As of March 1998
9
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION (Automotive version)
The 3874 group (automotive version) is designed for automotive body electronics control. Mitsubishi plans to expand the 3874 group (automotive version) as follows:
ROM/PROM size ............................................... 16 K to 60 K bytes RAM size .......................................................... 1024 to 2048 bytes
Packages
80P6S-A .................................. 0.65 mm-pitch plastic molded QFP
Memory Type
Support for mask ROM and One Time PROM versions
Memory Size Memory Expansion Plan of 3874 group (Automotive version)
ROM size (byte) 60K 56K 52K 48K 44K 40K 36K 32K 28K Mass product 24K 20K 16K M38747M6T Mass product M38747M4T 1024 RAM size (byte) 1536 2048 Mass product M38747MCT Mass product M38749EFT *Supported only PROM version shipped after writing
Products under development or planning : the development schedule and specification may be revised without notice. Planning products may be stopped during the development.
Fig. 7 Memory expansion plan (Automotive correspondence version) Currently planning products are listed below. Table 4 Support products Product name M38749EFT M38747MCT M38747M6T M38747M4T (P) ROM size (bytes) ROM size for User in ( ) 61440 (61310) 49152 (49022) 24576 (24446) 16384 (16254) RAM size (bytes) 2048 1048 80P6S-A Package Remarks One Time PROM version Mask ROM version As of March 1998
10
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU)
The 3874 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used.
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and the internal system clock selection bit etc. The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : Page 0 1 : Page 1 XCOUT drivability selection bit 0 : Low drive 1 : High drive Port XC switch bit 0 : I/O port function 1 : XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : = f(XIN)/2 (high-speed mode) 0 1 : = f(XIN)/8 (middle-speed mode) 1 0 : = f(XCIN)/2 (low-speed mode) 1 1 : = f(XIN) (double-speed mode)
Note: When setting b7 to b3, refer to notes of Figure 71.
Fig. 8 Structure of CPU mode register
11
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
Zero Page
Access to this area with only 2 bytes is possible in the zero page addressing mode.
Special Page RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts. Access to this area with only 2 bytes is possible in the special page addressing mode.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size (bytes) Address XXXX16
000016 SFR area 004016 010016 020016 030016 XXXX16 Not used YYYY16 Reserved ROM area Serial I/O3 automatic transfer RAM area Zero page
1024 1536 2048
043F16 063F16 083F16 RAM
ROM area
ROM size (bytes) Address YYYY16 Address ZZZZ16
(128 bytes)
16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440
C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016
C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016
ZZZZ16
ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Special page
Reserved ROM area
Fig. 9 Memory map diagram
12
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D) Port P9 (P9) Serial I/O3 register/Transfer counter (SIO3) Serial I/O3 control register 1 (SIO3CON1) Serial I/O3 control register 2 (SIO3CON2) Serial I/O3 control register 3 (SIO3CON3) Serial I/O3 automatic transfer data pointer (SIO3DP) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register (SIO2CON) Watchdog timer control register (WDTCON) Serial I/O2 register (SIO2)
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916
Timer X (low-order) (TXL) Timer X (high-order) (TXH) Timer Y (low-order) (TYL) Timer Y (high-order) (TYH) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer X mode register (TXM) Timer Y mode register (TYM) Timer 123 mode register (T123M)
002A16 Communication mode register (BUSM) 002B16 Transmit control register (TXDCON) 002C16 Transmit status register (TXDSTS) 002D16 Receive control register (RXDCON) 002E16 Receive status register (RXDSTS) 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Bus interrupt source discrimination control register (BICOND) Control field selection register (CFSEL) Control field register (CF) Transmit/Receive FIFO (TRFIFO) PULL UP register (PULLU) A-D control register (ADCON) A-D/D-A conversion register (AD) Interrupt source discrimination register 2 (IREQD2) Interrupt source discrimination control register 2 (ICOND2) Interrupt source discrimination register 1 (IREQD1) Interrupt source discrimination control register 1 (ICOND1) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
Fig. 10 Memory map of special function register (SFR)
13
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
The I/O ports P0-P8 have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that bit, that pin becomes an output pin. Table 5 I/O port function (1) Pin P00-P07 Name Port P0 Input/Output Input/output, individual bits Input/output, individual bits Input/output, individual bits Input/output, individual bits Input/output, individual bits I/O Structure *CMOS compatible input level *CMOS 3-state output *CMOS compatible input level *CMOS 3-state output *CMOS compatible input level *CMOS 3-state output *CMOS compatible input level *CMOS 3-state output *CMOS compatible input level *CMOS 3-state output
If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.
Non-Port Function
Related SFRs
Ref.No. (1)
P10-P17
Por t P1
P20-P27
Port P2
* K ey i n p u t ( k ey - o n wake-up) interrupt input
*PULL UP register
(2)
P30-P37
Port P3
*CPU mode register
(1)
P40/XCOUT P41/XCIN P42/INT1, P43/INT2 P44/RXD P45/TXD P46/SCLK1 P47/SRDY1 P50/TOUT P51/INT3, P52/INT4, P53/INT5 P54/CNTR0 P55/CNTR1 P56/RTP0 P57/RTP1 P60/AN0- P67/AN7
Port P4
*Sub-clock generating circuit I/O *External interrupt input *Serial I/O1 function I/O
*CPU mode register *Interrupt edge selection register *Serial I/O1 control register *Serial I/O1 status register *UART control register *PULL UP register *Timer 123 mode register *Interrupt edge selection register *Timer X mode register *Timer Y mode register *Timer X mode register *Timer Y mode register *A-D control register
(3) (4) (5) (6) (7) (8) (9) (10) (5)
Por t P5
Input/output, individual bits
*CMOS compatible input level *CMOS 3-state output
*Timer 2 output *External interrupt input
*Timer X function I/O *Timer Y function I/O *Real time port function output *Real time port function output *A-D converter input
(11) (12) (13)
Port P6
Input/output, individual bits
*CMOS compatible input level *CMOS 3-state output
(14)
14
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6 I/O port function (2) Pin P70/SIN2 P71/SOUT2 P72/SCLK2 P73,P74 P75/BUSOUT P76/BUSIN *Data link layer communication control I/O *Communication mode register *Transmit control register *Transmit status register *Receive control regiser *Receive status register *Bus interrupt source discrimination control register *Control field selection register *Control field register *Transmit/Receive FIFO P77/ADT P80/DA P81 P82/SOUT3 P83/SIN3 P84/SCLK3 P85/SRDY3 P86/SBUSY3 P87/SSTB3 Port P8 Input/output, individual bits *CMOS compatible input level *CMOS 3-state output *A-D trigger input *D-A function output *A-D control register *A-D control register (20) (21) (1) *Serial I/O3 function I/O *Serial I/O3 register/ Transfer counter *Serial I/O3 control register 1 *Serial I/O3 control register 2 *Serial I/O3 control register 3 *Serial I/O3 automatic transfer data pointer Port P9 Input *CMOS compatib le input level *External interrupt input *Interrupt edge selection register (22) (23) (24) (25) (26) (27) Name Por t P7 Input/Output Input/output, individual bits I/O Function *CMOS compatible input level *CMOS 3-state output Non-Port Function *Serial I/O2 function I/O Related SFRs *Serial I/O2 control register *PULL UP register Ref.No. (15) (16) (17) (1) (18) (19)
P97/INT0
(28)
Note: Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.
15
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Pull-up Control
P20-P26, TXD, SCLK1, SOUT2, and SCLK2 can perform pull-up control by setting "1" to the pull-up register (address 003316). P20-P27's pull-up is valid in the input mode, and TXD, SCLK1, SOUT2, and SCLK2s' pull-up is valid in the output mode.
b7 b0 Pull-up register (PULLU : address 0033 16) P26, P27 pull-up P25 pull-up P22-P24 pull-up P20, P21 pull-up TXD, SCLK1 pull-up SOUT2, SCLK2 pull-up Not used (returns "0" when read) (Do not write "1" to these bits.) 0: No pull-up 1: Pull-up
Fig.11 Structure of Pull-up Register
16
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P0,P1,P3,P73,P74,P81
(2) Port P2
P2 pull-up
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Key input interrupt input
(3) Port P40
(4) Port P41
Port XC switch bit
Direction register
Port XC switch bit
Direction register
Data bus
Port latch
Data bus
Port latch
Oscillator Port P41 Port XC switch bit Sub-clock generating circuit input
(5) Ports P42,P43,P51,P52,P53
(6) Port P44
Serial I/O1 enable bit Receive enable bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
INT1-INT5 interrupt input
Serial I/O1 input
Fig. 12 Port block diagram (1)
17
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(7) Port P45
TXD pull-up P45/TXD P-channel output disable bit Serial I/O1 enable bit Transmit enable bit
Direction register
(8) Port P46
Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit
Direction register
SCLK1 pull-up
Data bus
Port latch
Data bus
Port latch
Serial I/O1 output
Serial I/O1 clock output Serial I/O1 clock input
(9) Port P47
Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit
Direction register
(10) Port P50
Direction register
Data bus
Port latch Data bus Port latch
Serial I/O1 ready output
TOUT output control bit Timer output
(11) Port P54
(12) Port P55
Direction register Direction register
Data bus
Port latch
Data bus
Port latch
Pulse output mode Timer output CNTR0 interrupt input Event count input Pulse width measurement gate input
CNTR1 interrupt input Event count input Reload input
Fig. 13 Port block diagram (2)
18
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(13) Ports P56, P57
(14) Port P6
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Real time port control bit Data for real time port
A-D converter input Analog input pin selection bit
(15) Port P70
Direction register
Data bus
Port latch
Serial I/O2 input
(16) Port P71
SOUT2 output signal in operating SCLK2 pin selection bit SOUT2 output control bit SOUT2 pin selection bit
Direction register
SOUT2 pull-up P-channel output disable bit
Data bus
Port latch
Serial I/O2 output
Fig. 14 Port block diagram (3)
19
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(17) Port P72
SCLK2 pull-up P71/SOUT2 * P72/SCLK2 P-channel output disable bit
SCLK2 pin selection bit
Direction register
Data bus
Port latch
Serial I/O2 clock output Serial I/O2 clock input
(18) Port P75
Data link layer communication control circuit valid signal (output from sub-CPU)
Direction register
(19) Port P76
Data link layer communication control circuit valid signal (output from sub-CPU)
Direction register
Data bus
Port latch
Data bus
Port latch
Data link layer communication control circuit transmit output
Data link layer communication control circuit receive input
(20) Port P77
(21) Port P80
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
ADT interrupt input When the direction register is "0," the schmidt input pin is connected to port.
D-A converter output D-A ON
Fig. 15 Port block diagram (4)
20
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(22) Port P82
P82/SOUT3 * P84/SCLK3 P-channel output disable bit SOUT3 output control bit Serial transfer selection bit Serial I/O disabled
Direction register
(23) Port P83
Transfer mode selection bit Serial transfer selection bit Serial I/O disabled
Direction register
Data bus Data bus Port latch
Port latch
Serial I/O3 input Serial I/O3 output
(24) Port P84
P82/SOUT3 * P84/SCLK3 Serial I/O3 synchronous P-channel output disable bit clock selection bit Internal synchronous clock Serial transfer selection bit Serial I/O disabled
Direction register
(25) Port P85
P85/SRDY3 * P86/SBUSY3 pin control bit SRDY3 output P85/SRDY3 * P86/SBUSY3 pin control bit SRDY3 input Serial transfer selection bit Serial I/O disabled
Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O3 clock output Serial I/O3 clock input
Serial I/O3 ready output Serial I/O3 ready input
(26) Port P86
P85/SRDY3 * P86/SBUSY3 pin control bit SBUSY3 output P85/SRDY3 * P86/SBUSY3 pin control bit SBUSY3 input Serial transfer selection bit Serial I/O disabled
Direction register
(27) Port P87
Serial I/O3 synchronous clock selection bit SSTB3,SSTB3 output Serial I/O disabled
Direction register
Data bus
Port latch Data bus Port latch
Serial I/O3 busy output Serial I/O3 busy input
Fig. 16 Port block diagram (5)
21
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(28) Port P97
Data bus
INT0 interrupt input
Fig. 17 Port block diagram (6)
22
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by 27 sources: 10 external, 16 internal, and 1 software.
Interrupt Factor Determination
The interrupt request bit for each vector of "multiple factors/one vector interrupt" is set to "1" when the interrupt disable flag (I) is "0" and one of the factor interrupt enable bits is "1" and the corresponding factor interrupt request bit changes from "0" to "1". At this time, if the vector interrupt enable bit is "1", the interrupt occurs. (Note that the interrupt request bit for each vector and the factor interrupt request bit are both edge sense.) When 2 or more interrupt requests of interrupt factors assigned to one interrupt vector are generated at the same time, confirm the interrupt request bits for each interrupt factor assigned to the vector, and process according to the priority. If the interrupt request bit for the interrupt factor is "1" and the interrupt enable bits for interrupt factor and each vector are both "1"; for example, when an interrupt of another interrupt factor assigned to the same vector occurs while an interrupt processing routine is executed, the interrupt occurs again after returning. Clear the interrupt request bits which are not necessary or which have been already processed before executing the interrupt flag clear (CLI) or interrupt processing routine return (RTI) instruction. The interrupt request bits for each interrupt factor are not cleared by hardware after an interrupt vector address branching. Clear these bits by software in the interrupt processing routine. Use the LDM, STA, etc. instructions to do it. Do not use the read- modifywrite instruction; for example, the CLB.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. The interrupt control circuit consists of two types of interrupts: "one factor/one vector interrupt" and "multiple factors/one vector interrupt". The configuration is shown in Figure 18.
Interrupt Operation
When an interrupt occurs, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit for each vector is cleared. (The corresponding interrupt request bit for each interrupt factor is not cleared.) 3. The interrupt jump destination address of interrupt which has the highest priority is loaded to the program counter.
s Notes
When the active edge of an external interrupt (INT0-INT5, CNTR0, CNTR1) is set, the corresponding interrupt request bit may also be set. Therefore, take following sequence: (1) Disable the external interrupt which is selected. (2) Change the active edge in interrupt edge selection register (in case of CNTR0: Timer X mode register; in case of CNTR1: Timer Y mode register). (3) Clear the set interrupt request bit to "0". (4) Enable the external interrupt which is selected.
23
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 7 Interrupt vector addresses and priority Interrupt Sources Reset (Note 2) INT0 INT1 Receive bus interrupt source 1 Receive bus interrupt source 2 Receive bus interrupt source 3 Transmit bus interrupt source 1 Transmit bus interrupt source 2 Transmit bus interrupt source 3 Timer X Timer Y Timer 2 Timer 3 INT2 Serial I/O3 interrupt CNTR0 CNTR1 Timer 1 INT3 INT4 INT5 ADT 15 FFE116 FFE016 6 7 8 9 10 11 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 5 FFF516 FFF416 Priority 1 2 3 4 Vector Addresses (Note 1) High Low FFFD16 FFFC16 FFFB16 FFFA16 FFF916 FFF716 FFF816 FFF616 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input When receive bus source 1 request bit "1" from "0" When receive bus source 2 request bit "1" from "0" When receive bus source 3 request bit "1" from "0" When transmit bus source 1 request bit "1" from "0" When transmit bus source 2 request bit "1" from "0" When transmit bus source 3 request bit "1" from "0" At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow interrupt becomes interrupt becomes interrupt becomes interr upt becomes interr upt becomes interr upt becomes The condition which the transmit bus interrupt factor request bit becomes "1" is defined according to each communication protocol specification confirmation. Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) The condition which the receive bus interrupt factor request bit becomes "1" is defined according to each communication protocol specification confirmation.
At detection of either rising or falling edge of INT2 input At completion of serial I/O3 data transmission/reception At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer 1 underflow At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At detection of either rising or falling edge of INT5 input At falling of ADT pin input
12 13 14
FFE716 FFE516 FFE316
FFE616 FFE416 FFE216
External interrupt (active edge selectable) Valid only when serial I/O3 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid only when ADT interrupt is selected External interrupt (falling valid) Valid only when A-D converter interrupt is selected Valid only when serial I/O2 is selected External interrupt (falling valid) Valid only when serial I/O1 is selected Valid only when serial I/O1 is selected Non-maskable software interrupt
A-D converter Serial I/O2 interrupt Key input (keyon wake-up) Serial I/O1 receive Serial I/O1 transmit BRK instruction
At completion of A-D converter At completion of serial I/O2 data transmission/reception At falling of port P20 to P25 (at input) input logical level AND At completion of serial I/O1 data reception At completion of serial I/O1 transmission shift or when transmission buffer is empty At BRK instruction execution
16
FFDF16
FFDE16
17
FFDD16
FFDC16
Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: Either ADT interrupt or A-D converter interrupt can be used. Both ADT interrupt and A-D converter interrupt cannot be used.
24
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Multiple factors/one vector interrupt
Interrupt request of interrupt factor: IDREQINYZ Clear instruction by user program Interrupt enable bit for interrupt factor SYNC Internal system clock STP Instruction Clear instruction by user program Interrupt disable flag (I) D T R Q Interrupt request bit for interrupt factor Interrupt request from multiple factors: IDREQY D D T R Interrupt request get control signal: IREQGET Hardware clear signal by occurrence of interrupt Clear instruction by user program Interrupt enable bit for each vector Q T R Q Interrupt request bit for each vector: IREQY D T R Q
One factor/one vector interrupt
Interrupt request bit for each vector: IREQX D Interrupt Request IREQINX T R Q D T R Q
Interrupt request get control signal: IREQGET Hardware clear signal by occurrence of interrupt Clear instruction by user program Interrupt enable bit for each vector
Interrupt occurrence
Interrupt disable flag (I) BRK Instruction Reset
Fig.18 Interrupt control diagram
25
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing to Interrupt Request Acceptance
The cycle number of internal system clock required from occurrence to acceptance of an interrupt request depends on the type of interrupt: "multiple factors/one vector" or "one factor/one vector". For "one factor/one vector interrupt", the CPU starts processing the management after interrupt acceptance at the next instruction execution timing (rising edge of SYNC signal) immediately after the interrupt request is generated. For "multiple factors/one vector interrupt", the CPU starts processing the management after interrupt acceptance at the second instruction execution timing (rising edge of SYNC signal) after the interrupt request for interrupt factor determination is generated. In other words, "multiple factors/one vector interrupt" required one instruction execution cycle number (2 to 16 cycles of internal system clock) more than that of "one factor/one vector interrupt" to begin the interrupt sequence. Figure 18 shows the interrupt control diagram and Figure 19 shows the timing from occurrence to acceptance of interrupt request. For "one factor/one vector interrupt", the interrupt request is generated at Timing (A) and the processing after acceptance begins at Timing (B). For "multiple factors/one vector interrupt", the interrupt factor determination request is generated at Timing (C), the interrupt request is generated at Timing (D), and the processing after acceptance begins at Timing (E).
26
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal system clock SYNC Address bus Data bus
PC Not used
S,SPS
S-1,SPS
S-2,SPS
PCH
PCL
PS
Interrupt request signal input IREQINx Interrupt request signal IREQx IRGET Management after interrupt acceptance (B)
(A)
(a) One factor/one vector interrupt
Internal system clock
SYNC Address bus Data bus Interrupt source determination request signal input IDREQINY Interrupt request signal from interrupt source IDREQY Interrupt request signal IREQY (C) (D) 2 to 16 cycles of (b) Multiple factors/one vector interrupt
PC
Not used
IRGET
Management after interrupt acceptance
(E)
Fig.19 Timing from occurrence to acceptance of interrupt
27
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit INT2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit INT5 active edge selection bit Not used (returns "0" when read)
0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) INT2 interrupt request bit CNTR0, serial I/O3 interrupt request bit CNTR1 interrupt request bit Timer 1 interrupt request bit INT3, INT4, INT5 interrupt request bit ADT/A-D converter, serial I/O2 interrupt request bit Key input, serial I/O1 receive, serial I/O1 transmit interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 2 (ICON2 : address 003F16) INT2 interrupt enable bit CNTR0, serial I/O3 interrupt enable bit CNTR1 interrupt enable bit Timer 1 interrupt enable bit INT3, INT4, INT5 interrupt enable bit ADT/A-D converter, serial I/O2 interrupt enable bit Key input, serial I/O1 receive, serial I/O1 transmit interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit) 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt source discrimination control register 1 (ICOND1 : address 003916) INT3 interrupt enable bit INT4 interrupt enable bit INT5 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Key input interrupt enable bit Serial I/O2 interrupt enable bit ADT/A-D converter interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled b7 b0 Interrupt source discrimination control register 2 (ICOND2 : address 003716) CNTR0 interrupt enable bit Serial I/O3 interrupt enable bit Not used (return "0" when read) 0 : Interrupt disabled 1 : Interrupt enabled
b7
b0
Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit Receive bus interrupt request bit Transmit bus interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit
0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Receive bus interrupt enable bit Transmit bus interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit
0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt source discrimination register 1 (IREQD1 : address 003816) INT3 interrupt request bit INT4 interrupt request bit INT5 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Key input interrupt request bit Serial I/O2 interrupt request bit ATD/A-D converter interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt source discrimination register 2 (IREQD2 : address 003616) CNTR0 interrupt request bit Serial I/O3 interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued
Fig. 20 Structure of interrupt-related registers
28
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key Input Interrupt
A Key input interrupt request is generated by applying "L" level to any pin of por t P2 that have been set to input mode. In other words, it is generated when AND of input level goes from "1" to "0".
An example of using a key input interrupt is shown in Figure 21, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P20-P24.
Port PXx "L" level output PULL UP register Bit 0 = "0"
V VV
P27 output
Port P27 direction register = "1" Port P27 latch
Key input interrupt request
Port P26 direction register = "1"
V VV
P26 output
Port P26 latch
PULL UP register Bit 1 = "0"
V VV
Port P25 direction register = "1"
P25 output
Port P25 latch
PULL UP register Bit 2 = "1"
V VV
Port P24 direction register = "0"
P24 input
Port P24 latch
Port P23 direction register = "0"
V VV
P23 input
Port P23 latch
Port P2 Input reading circuit
Port P22 direction register = "0"
V VV
P22 input
Port P22 latch
PULL UP register Bit 3 = "1"
V VV
Port P21 direction register = "0"
P21 input
Port P21 latch
V
Port P20 direction register = "0"
VV
P20 input
Port P20 latch
V
P-channel transistor for pull-up
VV CMOS output buffer
Fig. 21 Connection example when using key input interrupt and port P2 block diagram
29
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
The 3874 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches "0016" or "000016", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit cor-
responding to that timer is set to "1". Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation.
Real time port control bit "1" P56/RTP0 QD P56 data for real time port Latch P56 direction register "0" P56 latch Real time port control bit "1" QD P57/RTP1 Latch P57 direction register "0" P57 latch XIN/16 (XCIN/16 in = XCIN/2) CNTR0 active edge switch bit "0"
Timer X operating mode bit "00","01","11"
Data bus
P57 data for real time port Real time port control bit "0" "1" Timer X stop control bit
Timer X (low) latch (8) Timer X (low) (8)
Timer X mode register write signal Timer X write control bit
Timer X (high) latch (8) Timer X (high) (8)
P54/CNTR0
"1" Pulse width measurement mode CNTR0 active edge switch bit "0" "1" P54 direction register P54 latch Pulse output mode
"10"
Timer X interrupt
Pulse output mode QS T Q
Pulse width HL continuously measurement mode Rising edge detection Falling edge detection Period measurement mode
P55/CNTR1
CNTR1 active edge switch bit "0" "1"
XIN/16 (XCIN/16 in = XCIN/2) Timer Y stop control bit "00","01","11"
Timer Y (low) latch (8) Timer Y (low) (8) Timer Y (high) latch (8) Timer Y (high) (8)
Timer Y interrupt
"10" Timer Y operating mode bit Timer 1 interrupt
XIN/16 (XCIN/16 in = XCIN/2) Timer 1 count source selection bit "0" Timer 1 latch (8) XCIN Timer 1 (8) "1"
Timer 2 count source selection bit Timer 2 latch (8) "0" Timer 2 (8) "1" XIN/16 (XCIN/16 in = XCIN/2)
Timer 2 write control bit
Timer 2 interrupt
TOUT output active edge switch bit "0" P50/TOUT "1" P50 latch P50 direction register TOUT output control bit XIN/16(XCIN/16 in = XCIN/2)
TOUT output control bit QS T Q "0" Timer 3 latch (8) Timer 3 (8) "1" Timer 3 count source selection bit Timer 3 interrupt
Fig. 22 Timer block diagram
30
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register.
b7 b0 Timer X mode register (TXM : address 002716) Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid P56 data for real time port P57 data for real time port Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Count at rising edge in event counter mode Start from "H" output in pulse output mode Measure "H" pulse width in pulse width measurement mode Falling edge active for CNTR0 interrupt 1 : Count at falling edge in event counter mode Start from "L" output in pulse output mode Measure "L" pulse width in pulse width measurement mode Rising edge active for CNTR0 interrupt Timer X stop control bit 0 : Count start 1 : Count stop
(1) Timer Mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in system clock = XCIN/ 2).
(2) Pulse Output Mode
Each time the timer underflows, a signal output from the CNTR0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the direction register of corresponding port to output mode.
(3) Event Counter Mode
The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode.
(4) Pulse Width Measurement Mode
The count source is f(XIN)/16 (or f(XCIN)/16 in system clock = XCIN/2. If CNTR0 active edge switch bit is "0", the timer counts while the input signal of CNTR0 pin is at "H". If it is "1", the timer counts while the input signal of CNTR0 pin is at "L".
s Notes
q Timer X write control If the timer X write control bit is "1", when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the timer X write control bit is "0", when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. When the value is to be written in latch only, if the value is written to the latch at timer X underflows, the value is consequently loaded in the timer X and the latch at the same time. Unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. q CNTR0 interrupt active edge selection CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. q Real time port control Data for the real time port are output from ports P56 and P57 each time the timer X underflows. (However, if the real time port control bit is changed from "0" to "1", data are output independent of the timer X operation.) When the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode.
Fig. 23 Structure of timer X mode register
31
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
b7 b0 Timer Y mode register (TYM : address 002816) Not used (return "0" when read) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop
(1) Timer Mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in system clock = XCIN/ 2).
(2) Period Measurement Mode
CNTR1 interrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR1 pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR1 pin input signal is found by CNTR1 interrupt.
(3) Event Counter Mode
The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. Fig. 24 Structure of timer Y mode register
(4) Pulse Width HL Continuously Measurement Mode
CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode.
s Note
q CNTR1 interrupt active edge selection CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit.
32
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. q Timer 2 write control When the timer 2 write control bit is "1", and the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. When the timer 2 write control bit is "0", and the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. q Timer 2 output control An inversion signal from TOUT pin is output each time timer 2 underflows. In this case, set the port P50 direction register to the output mode.
b7 b0 Timer 123 mode register (T123M :address 002916) TOUT output active edge switch bit 0 : Start at "H" output 1 : Start at "L" output TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled Timer 2 write control bit 0 : Write data in latch and counter 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 1 count source selection bit 0 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) 1 : f(XCIN) Not used (return "0" when read)
s Note
q Timer 1 to timer 3 When the count source of timer 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is generated in count input of timer. If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3.
Note : Internal clock is f(XCIN)/2 in the low-speed mode.
Fig. 25 Structure of timer 123 mode register
33
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O Serial I/O1
Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation.
(1) Clock Synchronous Serial I/O1 Mode
Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to "1". For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register (address 001816).
Data bus Address 001816
Receive buffer register (RB)
Serial I/O1 control register
Address 001A16
Receive buffer full flag (RBF) Receive interrupt request (RI)
Clock control circuit
P44/RXD
Receive shift register
Shift clock P46/SCLK1
XIN
BRG count source selection bit 1/4
Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1)
Baud rate generator
1/4
Address 001C16
Falling-edge detector Clock control circuit
P47/SRDY1
F/F
Shift clock P45/TXD
Transmit shift register
Transmit buffer register (TB)
Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Address 001916
Serial I/O1 status register
Address 001816 Data bus
Fig. 26 Block diagram of clock synchronous serial I/O
Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial I/O1 output TXD Serial I/O1 input RXD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Receive enable signal SRDY1 Write signal to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection
TBE = 1 TSC = 0
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TXD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" .
Fig. 27 Operation of clock synchronous serial I/O1 function
34
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis-
ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received.
Data bus Address 001816
Receive buffer register OE Character length selection bit 7 bits STdetector Receive shift register 8 bits
Serial I/O control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16
P44/RXD
PE FE
SP detector Clock control circuit
UART control register Address 001B16
Serial I/O1 synchronous clock selection bit P46/SCLK1 BRG count source selection bit 1/4 Frequency division ratio 1/(n+1) Baud rate generator Address 001C16
ST/SP/PA generator
XIN
1/16 P45/TXD Character length selection bit
Transmit buffer register
Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916
Transmit shift register
Address 001816 Data bus
Fig. 28 Block diagram of UART serial I/O1
Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial I/O output TXD ST D0 TBE=0 TBE=1 D1 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1
V Generated
TSC=1V SP at 2nd bit in 2-stop-bit mode
Receive buffer read signal
RBF=1 Serial I/O input RXD ST D0 D1 SP ST D0
RBF=0
RBF=1
D1
SP
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes "1". 4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 29 Operation of UART serial I/O function
35
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Transmit Buffer/Receive Buffer Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is write-only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer register is "0".
[Serial I/O1 Status Register (SIO1STS)] 001916
The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O1 enable bit (bit 7) of the Serial I/O1 control register also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to "1", the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1".
[Serial I/O1 Control Register (SIO1CON)] 001A16
The serial I/O1 control register contains eight control bits for the serial I/O1 function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of a data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P45/TXD pin and P46/SCLK1 pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
36
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O1 status register (SIO1STS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE) =0 1: (OE) U (PE) U (FE) =1 Not used (returns "1" when read)
b7
b0
Serial I/O1 control register (SIO1CON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clockk synchronous serial I/O is selected. External clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P47 pin operates as ordinary I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44-P47 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P44-P47 operate as serial I/O pins)
b7
b0
UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return "1" when read)
Fig. 30 Structure of serial I/O1 control register
37
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O2
The Serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. When the internal clock is used, transfer is started by a write signal to the serial I/O2 register.
b7 b0
Serial I/O2 control register (SIO2CON : address 001D16) Serial I/O2 internal synchronous clock selection bits
b2 b1 b0
[Serial I/O2 Control Register (SIO2CON)] 001D16
The serial I/O2 control register contains 8 bits which control various serial I/O functions.
000 001 010 011 100 101 110 111
: f(XIN)/8 or f(XCIN)/8 : f(XIN)/16 or f(XCIN)/16 : f(XIN)/32 or f(XCIN)/32 : f(XIN)/64 or f(XCIN)/64 : : Do not set : f(XIN)/128 or f(XCIN)/128 : f(XIN)/256 or f(XCIN)/256
SOUT2 pin selection bit 0 : I/O port 1 : SOUT2 output pin P71/SOUT2 * P72/SCLK2 P-channel output disable bit In output mode 0 : CMOS 3 state 1 : N-channel open-drain output Serial I/O2 transfer direction selection bit 0 : LSB first 1 : MSB first SCLK2 pin selection bit 0 : External clock (SCLK2 function as an I/O port.) 1 : Internal clock (SCLK2 function as an output port.) SOUT2 output control bit (when serial data is not transferred) 0 : Output active 1 : High-impedance
Fig. 31 Structure of serial I/O2 control register
Data bus XCIN Main clock divide ratio selection bit CM7
Divider
1/8 1/16 1/32 1/64 1/128 1/256 Serial I/O2 internal synchronous clock selection bits
"10" XIN
"00,01,11" SCLK2 pin selection bit SCLK2 External clock "0" "0" P72/SCLK2 "1" SCLK2 pin selection bit P71/SOUT2 "0" P71 latch P72 latch "1"
Serial I/O2 counter (3)
Serial I/O2 interrupt request
"1" SOUT2 pin selection bit P70/SIN2 Serial I/O2 register (8)
Fig. 32 Block diagram of serial I/O2
38
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
qSerial I/O2 Operation When writing to the serial I/O2 register (001F16), the serial I/O2 counter is set to "7". After the write is completed, data is output from the SOUT2 pin each time the transfer clock goes from "H" to "L". In addition, each time the transfer clock goes from "L" to "H", the contents of the serial I/O2 register are shifted by 1 bit data is simultaneously received from the SIN2 pin. When selecting an internal clock as the transfer clock source, the serial I/O2 counter goes to "0" by counting the transfer clock 8 times, and the transfer clock stops at "H", and the interrupt request bit is set to "1". In addition, the SOUT2 pin becomes the high-impedance state after the completion of data transfer. (Bit 7 of the serial I/O2 control register does not go to "1" and only the SOUT2 pin becomes the high-impedance state.)
When selecting an external clock as the transfer clock source, the interrupt request bit is set when counting the transfer clock 8 times. However, the transfer clock does not stop, so that control the clock externally. The SOUT2 pin does not become the high-impedance state after completion of data transmit. In order to set the SOUT2 pin to the high-impedance state when selecting an exter nal clock, set "1" to bit 7 of the ser ial I/O2 control register after completion of data transmit. Also, make sure that SCLK2 is at "H" for this process. When the next data is transmitted (falling of transfer clock), bit 7 of the serial I/O2 control register goes to "0" and the SOUT2 pin goes to an active state.
Synchronous clock
Transfer clock
Serial I/O2 register write signal (Note) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 D0 D1 D2 D3 D4 D5 D6 D7
Note:
When selecting an internal clock after completion of data transmit, the S OUT2 pin becomes the high-impedance state.
Interrupt request bit set
Fig. 33 Serial I/O2 timing (LSB first)
39
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O3
Serial I/O3 has the following modes: 8-bit serial I/O, arbitrary bits from 1 to 256 serial I/O, up to 256-byte auto-transfer serial I/O. The 8-bit serial I/O transfers through serial I/O3 register (address 001316). The arbitrary bits and auto-transfer serial I/O modes transfer through the 256-byte serial I/O3 auto-transfer RAM (addresses 020016 to 02FF16).
The P85/SRDY3, P86/SBUSY3, and P87/SSTB3 pins all have the handshake input/output signal function and can perform active logic high/low selection.
Main address bus
Local address bus
Serial I/O3 automatic transfer RAM (020016 to 02FF16)
Main data bus
Local data bus
Address decoder
Serial I/O3 automatic transfer data pointer Transfer counter Serial I/O3 automatic transfer controller
XCIN Main clock division ratio selection bits
"10" Serial I/O3 automatic transfer interval register 1/4 1/8
XIN
"00,01,11"
P87 latch
1/16
Divider
"01"
1/32 1/64 1/128 1/256 1/512
"00,01"
(P87/SSTB3 pin control bits)
P87/SSTB3 P85/SRDY3* P86/SBUSY3 pin control bits P86/SBUSY3 P85/SRDY3* P86/SBUSY3 pin control bits P85/SRDY3
"10,11" P86 latch "0" "1"
P85 latch
"0" "1"
Serial I/O3 internal Serial I/O3 synchronous clock synchronous clock selection bits "00,10,11" selection bits Synchronous circuit
SCLK3
External clock P84 latch
"0"
Serial transfer status flag
Serial I/O3 interrupt request
P84/SCLK3
"1" "0"
Serial transfer selection bits P83 latch
Serial I/O3 counter
P82/SOUT3
"1" Serial transfer
selection bits P83/SIN3 Serial I/O3 register (8)
Fig. 34 Block diagram of serial I/O3
40
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0 Serial I/O3 control register 1 (SIO3CON1 (SC31) : address 001416) Serial transfer selection bits 00 : Serial I/O disabled (P82 to P87 pins are I/O ports.) 01 : 8-bit serial I/O 10 : Arbitrary bit serial I/O 11 : Automatic transfer serial I/O (8-bit) Serial I/O3 synchronous clock selection bits (P8 7/SSTB3 pin control bits) 00 : Internal synchronous clock (P87 pin is I/O port.) 01 : External synchronous clock (P87 pin is I/O port.) 10 : Internal synchronous clock (P87 pin is SSTB3 output.) 11 : Internal synchronous clock (P87 pin is SSTB3 output.) Serial I/O initialization bit 0 : Serial I/O initialization 1 : Serial I/O enabled Transfer mode selection bit 0 : Full duplex (transmit/receive) mode (P83 pin is SIN3 I/O.) 1 : Transmit-only mode (P83 pin is I/O port.) Serial I/O3 transfer direction selection bit 0 : LSB First 1 : MSB First Automatic transfer RAM transmit/receive address selection bit 0 : Transmit/Receive address match 200 16 to 2FF16 (Set automatic transfer data pointer to 0016 to FF16.) 1 : Transmit address 20016 to 27F16 Receive address 28016 to 2FF16 (Set automatic transfer data pointer to 0016 to 7F16.)
b7
b0 Serial I/O3 control register 2 (SIO3CON2 (SC32) : address 001516) P85/SRDY3 * P86/SBUSY3 pin control bits 0000: P85, P86 pins are I/O ports. 0001: Unused 0010: P85 pin is SRDY3 output, P86 pin is I/O port. 0011: P85 pin is SRDY3 output, P86 pin is I/O port. 0100: P85 pin is I/O port, P86 pin is SBUSY3 input. 0101: P85 pin is I/O port, P86 pin is SBUSY3 input. 0110: P85 pin is I/O port, P86 pin is SBUSY3 output. 0111: P85 pin is I/O port, P86 pin is SBUSY3 output. 1000: P85 pin is SRDY3 input, P86 pin is SBUSY3 output. 1001: P85 pin is SRDY3 input, P86 pin is SBUSY3 output. 1010: P85 pin is SRDY3 input, P86 pin is SBUSY3 output. 1011: P85 pin is SRDY3 input, P86 pin is SBUSY3 output. 1100: P85 pin is SRDY3 output, P86 pin is SBUSY3 input. 1101: P85 pin is SRDY3 output, P86 pin is SBUSY3 input. 1110: P85 pin is SRDY3 output, P86 pin is SBUSY3 input. 1111: P85 pin is SRDY3 output, P86 pin is SBUSY3 input. SBUSY3 output * SSTB3 output function selection bit (valid in automatic transfer mode) 0: Functions as signal for each 1-byte 1: Functions as signal for each transfer data set Serial transfer status flag 0: Serial transfer complete 1: Serial transfer in-progress SOUT3 output control bit (when serial data is not transferred) 0: Output active 1: Output high impedance P82/SOUT3 * P84/SCLK3 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode)
Fig. 35 Structure of serial I/O3 control registers 1 and 2
41
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
qSerial I/O3 Operation An internal or external synchronous clock can be selected as the serial transfer synchronous clock by the serial I/O3 synchronous clock selection bits of the serial I/O3 control register 1. Since the internal synchronous clock has its own built-in divider, 8 types of clocks can be selected by the serial I/O3 internal synchronous clock selection bits of the serial I/O3 control register 3. Either I/O port or handshake I/O signal function can be selected for the P85/SRDY3, P86/SBUSY3, and P87/SSTB3 pins by the serial I/O3 synchronous clock selection bits (P87/SSTB3 pin control bits) of the serial I/O3 control register 1 or the P85/SRDY3*P86/SBUSY3 pin control bits of the serial I/O3 control register 2. CMOS output or N-channel open-drain output can be selected for the SCLK3 and SOUT3 output pins by the P82/SOUT3 * P84/SCLK3 Pchannel output disable bit of the serial I/O3 control register 2. The SOUT3 output control bit of the serial I/O3 control register 2 can be used to select the status of the SOUT3 pin when serial data is not transferred; either output active or high-impedance. However, when selecting an external synchronous clock, the SOUT3 pin can go to the high-impedance status by setting the SOUT3 output control bit to "1" when SCLK3 input is at "H" after transfer completion. When the next serial transfer begins and SCLK3 goes to "L", the SOUT3 output control bit is automatically reset to "0" and goes to an output active status.
Regardless of selecting an internal or external synchronous clock, the serial transfer has both a full duplex mode as well as a transmit-only mode. These modes are set by the transfer mode selection bit of serial I/O3 control register 1. LSB first or MSB first can be selected for the input/output order of the serial transfer bit string by the serial I/O3 transfer direction selection bit of serial I/O3 control register 1. In order to use serial I/O3, the following process must be followed after all of the above set have been completed: First, select any one of 8-bit serial I/O, arbitrary bit serial I/O, or auto-transfer serial I/O by setting the serial transfer selection bits of the serial I/O3 control register 1. Then, enable the serial I/O by setting the serial I/O initialization bit of the serial I/O3 control register 1 to "1". Whether using an internal or external synchronous clock, set the serial I/O initialization bit to "0" when terminating a serial transfer during the transmission.
b7
b0 Serial I/O3 control register 3 (SIO3CON3 (SC33) : address 0016 16) Auto-transfer interval set bit 00000: 2 cycles of transfer clock 00001: 3 cycles of transfer clock : 11110: 32 cycles of transfer clock 11111: 33 cycles of transfer clock Written to latch Read from decrement counter Serial I/O3 internal synchronous clock selection bits 000: f(XIN)/4 or f(XCIN)/4 001: f(XIN)/8 or f(XCIN)/8 010: f(XIN)/16 or f(XCIN)/16 011: f(XIN)/32 or f(XCIN)/32 100: f(XIN)/64 or f(XCIN)/64 101: f(XIN)/128 or f(XCIN)/128 110: f(XIN)/256 or f(XCIN)/256 111: f(XIN)/512 or f(XCIN)/512
Fig. 36 Structure of serial I/O3 control register 3
42
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) 8-bit serial I/O mode
Address 001316 is the serial I/O3 register. When selecting an internal synchronous clock, serial transfer of the 8-bit serial I/O starts by the write signal to the serial I/O3 register (address 001316). The serial transfer status flag of the serial I/O3 control register 2 indicates the serial I/O3 register status. The flag is set to "1" by a serial I/O3 register write, which triggers a transfer start. After the 8-bit transfer is completed, the flag is reset to "0" and a serial I/O3 interrupt request occurs simultaneously. When an external synchronous clock is selected, the contents of the serial I/O3 register are continually shifted while the transfer clock inputs to SCLK3. In this case, control the clock externally.
(2) Auto-transfer serial I/O mode
Since read and write to the serial I/O3 register are controlled by the serial I/O3 automatic transfer controller, address 001316 functions as the transfer counter (in byte units). In order to make a serial transfer through the serial I/O3 automatic transfer RAM (addresses 020016 to 02FF16), it is necessary to set the serial I/O3 automatic transfer data pointer before transferring data. The automatic transfer data pointer set bits indicate the loworder 8 bits of the star t data stored address. The automatic transfer RAM transmit/receive address select bit can divide the 256-byte serial I/O3 automatic transfer RAM into two areas: 128byte transmit data area and 128-byte receive data area. When an internal synchronous clock is selected and any of the following conditions apply, the transfer interval between each 1-byte data can be set by the automatic transfer interval set bits of the serial I/O3 control register 3: 1. The handshake signal is not used. 2. The handshake signal's SRDY3 output, SBUSY3 output, and SSTB3 output are used independently. 3. The handshake signal's output is used in groups: SRDY3/SSTB3 output or SBUSY3/SSTB3. There are 32 values among 2 and 33 cycles of the transfer clock. When the automatic transfer interval setting is valid and SBUSY3 output is used, and the SBUSY3 and SSTB3 output function as sig-
nal for each transfer data set by the SBUSY3 output*SSTB3 output function selection bit, there is the transfer interval before the first data is transmitted/received, as well as after the last data is transmitted/received. When using SSTB3 output, regardless of the contents of the SBUSY3 output * SSTB3 output function selection bit, this transfer interval become 2 cycles longer than the value set for each 1-byte data. In addition, when using the combined output of SBUSY3 and SSTB3 as the signal for each transfer data set, the transfer interval after completion of transmission/receipt of the last data become 2 cycles longer than the set value. When selecting an exter nal synchronous clock, the automatic transfer interval cannot be set. After all of the above bit settings have been completed, and an internal synchronous clock has been selected, serial automatic transfer starts when the value of the number of transfer bytes, decremented by 1, is written to the transfer counter (address 001316). When an external synchronous clock is selected, write the value of the transfer bytes, decremented by 1, to the transfer counter, and input the transfer clock to SCLK3 after 5 or more cycles of internal clock . Set the transfer interval of each 1-byte data transmission to 5 or more cycles of the internal clock after the rising edge of the last bit of a 1-byte data. Regardless of internal or external synchronous clock, the automatic transfer data pointer and transfer counter are both decremented after receipt of each 1-byte data is completed and it is written to the automatic transfer RAM. The serial transfer status flag is set to "1" by writing to the transfer counter which triggers the start of transmission. After the last data is written to the automatic transfer RAM, the serial transfer status flag is set to "0" and a serial I/O3 interrupt request occurs simultaneously. The write values of the automatic transfer data pointer set bits and the automatic transfer interval set bits are kept in the latch. As a transfer counter write occurs, each value is transferred to its corresponding decrement counter.
b7
b0 Serial I/O3 automatic transfer data pointer (SIO3DP : address 001716) Automatic transfer data pointer set bits Indicates the low-order 8 bits of the address stored the start data on the serial I/O3 automatic transfer RAM. Write: kept in latch Read: from decrement counter
Fig. 37 Structure of serial I/O3 automatic transfer data pointer
43
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(3) Arbitrary bit serial I/O mode
Since read and write of the serial I/O3 register are controlled by the serial I/O3 automatic transfer controller, address 001316 functions as the transfer counter (in byte units). After the serial I/O3 automatic transfer data pointer and automatic transfer interval set bits have been set, and an internal synchronous clock selected, serial automatic transfer starts when the value of the number of transfer bits decremented by 1 is written to the transfer counter (address 001316), just as in the automatic transfer serial I/O. When selecting an external synchronous clock, write the value of the transfer bits decremented by 1 to the transfer counter, then input the transfer clock to SCLK3 after 5 or more cycles of internal clock . The transfer interval after each 8-bit data transfer must be 5 or more cycles of internal clock after the rising edge of the last bit of the 8-bit data. When selecting an internal synchronous clock, the automatic transfer interval can be specified regardless of the contents of the selected handshake signal. In this case, when the automatic transfer interval setting is valid and SBUSY3 output is used there are the transfer interval before the first data is transmitted/received, as well as after the last data is transmitted/received just as in the automatic transfer serial I/O mode. When using SSTB3 output, this transfer interval become 2 cycles longer than the value set for each 8-bit data. In addition, when using the combined output of SBUSY3 and SSTB3, the transfer interval after completion of transmission/receipt of the last data become 2 cycles longer than the set value.
When selecting an external synchronous clock, the automatic transfer interval cannot be specified. Regardless of internal or external synchronous clock, the automatic transfer data pointer is decremented after each 8-bit data is received and then written to the auto-transfer RAM. The transfer counter is decremented with the transfer clock. The serial transfer status flag is set to "1" by writing to the transfer counter which triggers the start of transmission. After the last data is written to the automatic transfer RAM, the serial transfer status flag is set to "0" and a serial I/O3 interrupt request occurs simultaneously. The write values of the automatic transfer data pointer set bits and the automatic transfer interval set bits are kept in the latch. As a transfer counter write occurs, each value is transferred to its corresponding decrement counter. If the last data does not fill 8 bits, the receive data stored in the serial I/O3 automatic transfer RAM become the closest MSB odd bit if the transfer direction select bit is set to LSB first, or the closest LSB odd bit if the transfer direction select bit is set to MSB first.
Automatic transfer RAM 2FF16 Automatic transfer data pointer 5216 25216 25116 25016 24F16 24E16 Transfer counter 0416
20016
SIN3 Serial I/O3 register
SOUT3
Fig. 38 Automatic transfer serial I/O operation
44
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Automatic transfer RAM (before transfer)
Automatic transfer data pointer 1516 21516 Transfer counter 0D16 21416 MSB 0 - 0 - 1 1 1 0 0 1 1 0 0 1 LSB 1 1 SOUT3 LSB first Transmit bit string Start bit 1 0 1 0 11 00110101 Odd bit
Automatic transfer RAM (after transfer)
Receive bit string Start bit 1 0 1 0 0 1 10010110 Odd bit SIN3 LSB first 21516 21416
MSB 1 1 0 0 0 1 1 0 0 0 1 1 1
LSB 0 -
-
*according to automatic transfer interval setting SCLK3 (Internal synchronous clock selected) SOUT3
SIN3
Serial transfer status flag
Transfer counter
D16
C16 B16 A16
9
8
7
6
5
4
3
2
1
0
Transfer counter write Automatic transfer data pointer Automatic transfer RAM Serial I/O3 register Serial I/O3 register Automatic transfer RAM * When using the SSTB3 output signal, this become 2 transfer clock cycles longer than the set interval.
1516
1416
Fig. 39 Arbitrary bit serial I/O operation
45
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Handshake Signal
q SSTB3 output signal The SSTB3 output is a signal to inform an end of transmission/reception to the serial transfer destination . The SSTB3 output signal can be used only when the internal synchronous clock is selected. In the initial status, that is, in the status in which the serial I/O initialization bit (b4) is reset to "0", the SSTB3 output goes to "L", and the SSTB3 output goes to "H". At the end of transmit/receive operation, when the data of the serial I/O3 register is all output from SOUT3, pulses which are the SSTB3 output of "H" and the SSTB3 output of "L" are output in the period of 1 cycle of the transfer clock. After that, each pulse is returned to the initial status in which SSTB3 output goes to "L" and the SSTB3 output goes to "H". Furthermore, after 1 cycle, the serial transfer status flag (b5) is reset to "0". In the automatic transfer serial I/O mode, whether making the SSTB3 output active at an end of each 1-byte data or after completion of transfer of all data can be selected by the SBUSY3 output * SSTB3 output function selection bit (b4 of address 001516) of serial I/O3 control register 2.
SBUSY3
SCLK3
SOUT3
Fig. 41 SBUSY3 input operation (internal synchronous clock) When the external synchronous clock is selected, input an "H" level signal into the SBUSY3 input and an "L" level signal into the SBUSY3 input in the initial status in which transfer is stopped. At this time, the transfer clocks to be input in SCLK3 become invalid. During serial transfer, the transfer clocks to be input in SCLK3 become valid, enabling a transmit/receive operation, while an "L" level signal is input into the SBUSY3 input and an "H" level signal is input into the SBUSY3 input. When changing the input values in to the SBUSY3 input and the SBUSY3 input in these operations, change them while the SCLK3 input is in a high state. When the high impedance of the SOUT3 output is selected by the SOUT3 output control bit (b6), the SOUT3 output becomes active, enabling serial transfer by inputting a transfer clock to SCLK3, while an "L" level signal is input into the SBUSY3 input and an "H" level signal is input into the SBUSY3 input.
SSTB3
SCLK3
SOUT3
SBUSY3
Fig. 40 SSTB3 output operation q SBUSY3 input signal The SBUSY3 input is a signal which receives a request for a stop of transmission/reception from the serial transfer destination. When the internal synchronous clock is selected, input an "H" level signal into the SBUSY3 input and an "L" level signal into the SBUSY3 input in the initial status in which transfer is stopped. When starting a transmit/receive operation, input an "L" level signal into the SBUSY3 input and an "H" level signal into the SBUSY3 input in the period of 1.5 cycles or more of the transfer clock. Then, transfer clocks are output from the SCLK3 output. When an "H" level signal is input into the SBUSY3 input and an "L" level signal into the SBUSY3 input after a transmit/receive operation is started, this transmit/receive operation are not stopped immediately and the transfer clocks from the SCLK3 output are not stopped until the specified number of bits is transmitted and received. The handshake unit of the 8-bit serial I/O is 8 bits and that of the arbitrary bit serial I/O is the bit number adding "1" to the set value to the transfer counter, and that of the automatic transfer serial I/O is 8 bits.
SCLK3 Invalid SOUT3
(Output high-impedance)
Fig. 42 SBUSY3 input operation (external synchronous clock) q SBUSY3 output signal The SBUSY3 output is a signal which requests a stop of transmission/reception to the serial transfer destination. In the automatic transfer serial I/O mode, regardless of the internal or external synchronous clock, whether making the SBUSY3 output active at transfer of each 1-byte data or during transfer of all data can be selected by the SBUSY3 output * SSTB3 output function selection bit (b4). In the initial status, that is, the status in which the serial I/O initialization bit (b4) is reset to "0", the SBUSY3 output goes to "H" and the SBUSY3 output goes to "L".
46
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When the internal synchronous clock is selected, in the 8-bit serial I/O mode and the automatic transfer serial I/O mode (SBUSY3 output function outputs in 1-byte units), the SBUSY3 output goes to "L" and the SBUSY3 output goes to "H" before 0.5 cycle (transfer clock) of the timing at which the transfer clock from the SCLK3 output goes to "L" at a start of transmit/receive operation. In the automatic transfer serial I/O mode (the SBUSY3 output function outputs all transfer data), the SBUSY3 output goes to "L" and the SBUSY3 output goes to "H" when the first transmit data is written into the serial I/O3 register (address 001316). When the external synchronous clock is selected, the SBUSY3 out-
put goes to "L" and the SBUSY3 output goes to "H" when transmit data is written into the serial I/O3 register to start a transmit operation, regardless of the serial I/O transfer mode. At termination of transmit/receive operation, the SBUSY3 output returns to "H" and the SBUSY3 output returns to "L", the initial status, when the serial transfer status flag is set to "0", regardless of selecting the internal or external synchronous clock. Furthermore, in the automatic transfer serial I/O mode (SBUSY3 output function outputs in 1-byte units), the SBUSY3 output goes to "H" and the SBUSY3 output goes to "L" each time 1-byte of receive data is written into the automatic transfer RAM.
SBUSY3
SBUSY3
Serial transfer status flag
Serial transfer status flag
SCLK3
SCLK3
Write to Serial I/O3 register
SOUT3
Fig. 43 SBUSY3 output operation (internal synchronous clock, 8-bits serial I/O)
Fig. 44 SBUSY3 output operation (external synchronous clock, 8-bits serial I/O)
Automatic transfer interval SCLK3
Serial I/O3 register Automatic transfer RAM Automatic transfer RAM Serial I/O3 register
SBUSY3
Serial transfer status flag
SOUT3
Fig. 45 SBUSY3 output operation in automatic transfer serial I/O mode (internal synchronous clock, SBUSY3 output function outputs each 1-byte)
47
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
q SRDY3 output signal The SRDY3 output is a transmit/receive enable signal which informs the serial transfer destination that transmit/receive is ready. In the initial status, that is, when the serial I/O initialization bit (b4) is reset to "0", the SRDY3 output goes to "L" and the SRDY3 output goes to "H". After transmitted data is stored in the serial I/O3 register (address 001316) and a transmit/receive operation becomes ready, the SRDY3 output goes to "H" and the SRDY3 output goes to "L". When a transmit/receive operation is started and the transfer clock goes to "L", the SRDY3 output goes to "L" and the SRDY3 output goes to "H". q SRDY3 input signal The SRDY3 input signal becomes valid only when the SRDY3 input and the SBUSY3 output are used. The SRDY3 input is a signal for receiving a transmit/receive ready completion signal from the serial transfer destination. When the internal synchronous clock is selected, input a low level signal into the SRDY3 input and a high level signal into the SRDY3 input in the initial status in which the transfer is stopped.
When an "H" level signal is input into the SRDY3 input and an "L" level signal is input into the SRDY3 input for a period of 1.5 cycles or more of transfer clock, transfer clocks are output from the SCLK3 output and a transmit/receive operation is started. After the transmit/receive operation is started and an "L" level signal is input into the SRDY3 input and an "H" level signal into the SRDY3 input, this operation cannot be immediately stopped. After the specified number of bits are transmitted and received, the transfer clocks from the SCLK3 output is stopped. The handshake unit of the 8-bit serial I/O and that of the automatic transfer serial I/O are of 8 bits. That of the arbitrary bit serial I/O is the bit number adding "1" to the set value to the transfer counter. When the external synchronous clock is selected, the SRDY3 input becomes one of the triggers to output the SBUSY3 signal. To start a transmit/receive operation (SBUSY3 output to "L", SBUSY3 output to "H"), input an "H" level signal into the SRDY3 input and an "L" level signal into the SRDY3 input, and also write transmit data into the serial I/O3 register.
Transfer interval SCLK3
Automatic transfer interval
Transfer interval
Serial I/O3 register Automatic transfer RAM Automatic transfer RAM Serial I/O3 register
SBUSY3
Serial transfer status flag
SOUT3
Fig. 46 SBUSY3 output operation in arbitrary bit serial I/O mode (internal synchronous clock)
SRDY3
SRDY3
SCLK3
SCLK3
Write to serial I/O3 register
SOUT3
Fig. 47 SRDY3 Output Operation
Fig. 48 SRDY3 Input Operation (internal synchronous clock)
48
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A:
SCLK3 SRDY3 SBUSY3 SCLK3 SRDY3 SBUSY3
Write to serial I/O3 register
SRDY3
SBUSY3
A:
Internal synchronous clock selection
B:
External synchronous clock selection
SCLK3
B:
Write to serial I/O3 register
Fig. 49 Handshake operation at serial I/O3 mutual connecting (1)
A:
SCLK3 SRDY3 SBUSY3 SCLK3 SRDY3 SBUSY3
Write to serial I/O3 register
SRDY3
SBUSY3
A:
Internal synchronous clock selection
B:
External synchronous clock selection
SCLK3
B:
Write to serial I/O3 register
Fig. 50 Handshake operation at serial I/O3 mutual connecting (2)
49
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D ATA L I N K L AY E R C O M M U N I C AT I O N CONTROL CIRCUIT
The 3874 Group has a built-in data link layer communication control circuit. This data link layer communication control circuit is applicable for multi-master serial bus communication control used only with data lines through an external driver/receiver. The data link layer communication control circuit consists of following. *Communication mode register (address 002A16) *Transmit control register (address 002B16) *Transmit status register (address 002C16) *Receive control register (address 002D16) *Receive status register (address 002E16) *Bus interrupt factor determination control register (address 002F16) *Control field select register (address 003016) *Control field data register (address 003116) *Transmit/Receive FIFO (address 003216) This function is realized by hardware and firmware so that communication protocol can be partially modified according to the user's specification. The following are the standard communication rate and functions which the data link layer communication control circuit can perform. *Communication rate: Approx. 40 kbps The communication rate depends on frame or bit protocol. *Synchronous method: Half-duplex asynchronous *Modification method: PWM method, NRZ, etc. *Communication functions: Bus arbitration (CSMA/CD method, etc.) Error detection (parity, acknowledge, CRC, etc.) Frame, data retry The transmission signal is output from the BUSOUT pin and input to the BUSIN pin. Detailed specifications for communication protocol, bit assignment, function, etc. of each register are defined according to each communication protocol specification confirmation.
50
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data Bus Bus interrupt source control signal Bus interrupt source determination control register (address 002F 16)
Control field selection register (address 0030 16) Local address Control field register (address 0031 16) Local data bus
To interrupt request register
* Register crowd 14 bytes Local address (addresses 00 16 to 0D16)
Communication mode register (address 002A 16) Bus interrupt request signal Transmit control register (address 002B 16)
Transmit status register (address 002C 16)
Receive control register (address 002D 16)
Receive status register (address 002E 16)
Transmit/Receive FIFO (address 0032 16) Transmit FIFO (8 bytes) Receive FIFO (16 bytes)
BUSIN/BUSOUT input/output control circuit * Each register name is defined according to the communication protocol specifications. BUSIN BUSOUT
Fig. 51 Data link layer communication control circuit block example
51
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Communication Mode Register (BUSM)] 002A16
The communication mode register (address 002A16) has 6 bits and consists of all the control bits for the communication mode.
b7
b0 Communication mode register (BUSM : address 002A16)
Arbitrary bits: defined according to each communication protocol specification confirmation.
Not used (Always write "00" to these bits.)
Fig. 52 Structure of communication mode register
52
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Transmit Control Register (TXDCON)] 002B16
The transmit control register (address 002B16) has 7 bits and consists of the transmit control and transmit status flags.
[Transmit Status Register (TXDSTS)] 002C16
The transmit status register (address 002C16) has 8 bits and consists of the transmit error flag and transmit interrupt request flag.
b7
b0 Transmit control register (TXDCON : address 002B16) Arbitrary bits: defined according to each communication protocol specification confirmation.
Not used (return "0" when read)
Arbitrary bits: defined according to each communication protocol specification confirmation.
Fig. 53 Structure of transmit control register
b7
b0 Transmit status register (TXDSTS : address 002C16) Arbitrary bits: defined according to each communication protocol specification confirmation. Transmit bus Interrupt source 1 request bit Transmit bus Interrupt source 2 request bit Arbitrary bits: defined according to each communication protocol specification confirmation.
Transmit bus Interrupt source 3 request bit
Note: Bits 0 to 3, bit 5, and bit 7 can be cleared only by software. When a transmit bus interrupt source request bit is "1," an interrupt request occurs. The name and function of each transmit bus interrupt source is defined according to the communication protocol specification confirmation.
Fig. 54 Structure of transmit status register
53
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Receive control register (RXDCON)] 002D16
The receive control register has 7 bits and consists of the receive control and receive status flags.
[Receive status register (RXDSTS)] 002E16
The receive status register has 8 bits and consists of the receive error flag and receive interrupt request flags.
b7
b0 Receive control register (RXDCON : address 002D16) Arbitrary bits: defined according to each communication protocol specification confirmation.
Not used (return "0" when read)
Arbitrary bits: defined according to each communication protocol specification confirmation.
Fig. 55 Structure of receive control register
b7
b0 Receive status register (RXDSTS : address 002E16) Arbitrary bits: defined according to each communication protocol specification confirmation. Receive bus interrupt source 1 request bit Receive bus interrupt source 2 request bit Arbitrary bits: defined according to each communication protocol specification confirmation.
Receive bus interrupt source 3 request bit
When a receive bus interrupt source request bit is "1", an interrupt request occurs. The name and function of each receive bus interrupt source is defined according to the communication protocol specification confirmation.
Fig. 56 Structure of receive status register
54
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Control field selection register (CFSEL)] 003016 [Control field register (CF)] 003116
The control field data select the control field selection register (address 003016) value as the pointer. The data can be confirmed
and changed by a read/write of the control field register (address 003016). For example, when reading/writing the local address "0016," the control field selection register is set to "0016" and the control field register is read/written.
b7
b0 Control field selection register (CFSEL : address 003016) Control field selection bits b3 b2 b1 b0 0000: 0001: 0010: 0011: 0100: 0101: 0110: Arbitrary bits: defined according to each communication 0111: protocol specification confirmation. 1000: 1001: 1010: 1011: 1100: 1101: 1 1 1 0 : Disabled 1 1 1 1 : Disabled Not used (write "0" to these bits.)
Fig. 57 Structure of control field selection register
55
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Bus interrupt source determination control register (BICOND)] 002F16
The bus interrupt source determination control register (address 002F16) has 6 bits and controls bus-related interrupts. Refer to
the section concerning interrupts for details about priority and vector addresses.
b7
b0 Bus interrupt source determination control register (BICOND : address 002F16) Transmit bus interrupt source 1 enable bit Transmit bus interrupt source 2 enable bit Not used (return "0" when read) Transmit bus interrupt source 3 enable bit Receive bus interrupt source 1 enable bit Receive bus interrupt source 2 enable bit Receive bus interrupt source 3 enable bit Not used (return "0" when read)
0: Interrupt disabled 1: Interrupt enabled The name and function of each transmit/receive bus interrupt source is defined according to the communication protocol specification confirmation.
Fig. 58 Structure of bus interrupt source determination control register
56
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER [A-D/D-A Conversion Register (AD)] 003516
The A-D/D-A conversion register is a register (at reading) that contains the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read.
Note that the comparator is constructed linked to a capacitor, so set f(XIN) to at least 500 kHz during A-D conversion. Use a CPU system clock dividing the main clock XIN.
b7
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D/D-A conversion process. Bits 0 to 2 of this register select specific analog input pins. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at "0" during an A-D conversion, then changes to "1" when the A-D conversion is completed. Writing "0" to this bit starts the A-D conversion. When bit 5, which is the AD external trigger valid bit, is set to "1", this bit enables A-D conversion even by a falling edge of an ADT input. Set "0" (input port) to the direction register corresponding the ADT pin. Bit 6 is the interrupt source selection bit. Writing "0" to this bit, A-D conver ter interrupt request occurs at completion of A-D conversion. Writing "1" to this bit the interrupt request occurs at falling edge of an ADT input.
b0
A-D control register (ADCON : address 003416) Analog input pin selection bits 000: P60/AN0 001: P61/AN1 010: P62/AN2 011: P63/AN3 100: P64/AN4 101: P65/AN5 110: P66/AN6 111: P67/AN7 AD conversion completion bit 0: Conversion in progress 1: Conversion completed VREF input switch bit 0: OFF 1: ON AD external trigger valid bit 0: AD external trigger invalid 1: AD external trigger valid Interrupt source selection bit 0: Interrupt request at A-D conversion completed 1: Interrupt request at ADT input falling DA output enable bit 0: DA output disabled 1: DA output enabled
Comparison Voltage Generator
The comparison voltage generator divides the voltage between AVSS and VREF by 256, and outputs the divided voltages.
Channel Selector
The channel selector selects one of the input ports P67/AN7 to P60/AN0 and inputs it to the comparator.
Comparator and Control Circuit
The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D/ D-A conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD conversion interrupt request bit to "1".
Fig. 59 Structure of A-D control register
Data bus
b7 A-D control register P77/ADT 3
b0
P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 Channel selector Comparator
A-D control circuit
ADT/A-D interrupt request
A-D conversion register 8 Resistor ladder
AVSS
VREF
Fig. 60 Block diagram of A-D converter
57
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A CONVERTER
The 3874 group has an on-chip D-A converter with 8-bit resolution and 1 channel. The D-A conversion is performed by setting the value in the A-D/D-A conversion register. The result of D-A converter is output from DA pin by setting the DA output enable bits to "1". When using the D-A converter, the corresponding port direction register bit (P80/DA) should be set to "0" (input status). The output analog voltage V is determined by the value n (base 10) in the A-D/D-A conversion register as follows: V=VREF ! n/256 (n=0 to 255) Where VREF is the reference voltage. At reset, the D-A conversion registers are cleared to "0016", the DA output enable bits are cleared to "0", and P80/DA pin becomes high impedance. The DA output is not buffered, so connect an external buffer when driving a low-impedance load. When using D-A converter, set 4.0 V or more to VCC.
Data bus
D-A conversion register (8) DA output enable bit P80/DA
R-2R resistor ladder
Fig. 61 Block diagram of D-A converter
s Note
When reading the A-D/D-A conversion register, the A-D conversion result is read, and the set value for D-A conversion is not read.
DA output enable bit
"0" R R R R R R R 2R
P80/DA
"1" MSB
2R
2R
2R
2R
2R
2R
2R
2R LSB
D-A conversion register AVSS VREF
"0"
"1"
Fig. 62 Equivalent connection circuit of D-A converter
58
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and a 12-bit watchdog timer H.
Watchdog Timer Initial Value
Watchdog timer L is set to "FF16" and watchdog timer H is set to "FFF16" by writing to the watchdog timer control register or at a reset. Any write instruction that causes a write signal can be used, such as the STA, LDM, CLB, etc. Data can only be written to bits 6 and 7 of the watchdog control register. Regardless of the value written to bits 0 to 5, the above-mentioned value will be set to each timer.
When bit 6 of the watchdog timer control register is kept at "0", the STP instruction is enabled. When that is executed, both the clock and the watchdog timer stop. Count re-starts at the same time as the release of stop mode (Note). The watchdog timer does not stop while a WIT instruction is executed. In addition, the STP instruction is disabled by writing "1" to this bit again. When the STP instruction is executed at this time, it is processed as an undefined instruction, and an internal reset occurs. Once a "1" is written to this bit, it cannot be programmed to "0" again. The following shows the period between the write execution to the watchdog timer control register and the underflow of watchdog timer H. Bit 7 of the watchdog timer control register is "0": when XCIN = 32 kHz; 524 s when XIN = 6.4 MHz; 2.6 s Bit 7 of the watchdog timer control register is "1": when XCIN = 32 kHz; 2 s when XIN = 6.4 MHz; 10 ms
Note: The watchdog timer continues to count even while waiting for a stop release. Therefore, make sure that watchdog timer H does not underflow during this period.
Watchdog Timer Operations
The watchdog timer stops at reset and a countdown is started by the writing to the watchdog timer control register. An internal reset occurs when watchdog timer H underflows. The reset is released after its release time. After the release, the program is restarted from the reset vector address. Usually, write to the watchdog timer control register by software before an underflow of the watchdog timer H. The watchdog timer does not function if the watchdog timer control register is not written to at least once.
XCIN "10" Main clock division ratio selection bits (Note) XIN
"FF16" is set when watchdog timer control register is written to. "0" Watchdog timer L (8) 1/16 "00" "01" "11" "1" Watchdog timer H (12)
Data bus "FF16" is set when watchdog timer control register is written to.
Watchdog timer H count source selection bit
STP instruction disable bit STP instruction Reset circuit Reset release time wait Note: Either double-speed, high-speed, middle-speed, or low-speed mode is selected by bits 7 and 6 of the CPU mode register. Internal reset
RESET
Fig. 63 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register (WDTCON : address 001E16)
Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16
Fig. 64 Structure of Watchdog timer control register
59
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an "L" level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage should be between 3.0 V and 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (loworder byte). Make sure that the reset input voltage is 0.6 V or less for VCC of 3.0 V.
Poweron Power source voltage 0V Reset input voltage 0V (Note)
RESET
VCC
0.2VCC
Note : Reset release voltage ; Vcc=2.5 V
RESET
VCC Power source voltage detection circuit
Fig. 65 Reset circuit example
XIN
RESET
Internal reset
Reset address from the vector table
Address Data
?
?
?
?
FFFC ADL
FFFD
ADH,ADL
ADH
SYNC XIN : 40 to 56 clock cycles
Notes 1: The frequency relation of f(XIN) and f() is f(XIN)=8 * f(). 2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 66 Reset sequence
60
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address
Register contents
Address
Register contents
(1) (2) (3) (4) (5) (6) (7) (8) (9)
Port P0 Port P0 direction register Port P1 Port P1 direction register Port P2 Port P2 direction register Port P3 Port P3 direction register Port P4
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116
0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016
(31) Timer Y (low-order) (32) Timer Y (high-order) (33) Timer 1 (34) Timer 2 (35) Timer 3 (36) Timer X mode register (37) Timer Y mode register (38) Timer 123 mode register (39) Communication mode register (40) Transmit control register (41) Transmit status register (42) Receive control register (43) Receive status register (44) Bus interrupt source discrimination control register (45) Control field selection register (46) PULL UP register (47) A-D control register (48) Interrupt source discrimination register 2 (49) Interrupt source discrimination control register 2 (50) Interrupt source discrimination register 1 (51) Interrupt source discrimination control register 1 (52) Interrupt edge selection register (53) CPU mode register (54) Interrupt request register 1 (55) Interrupt request register 2 (56) Interrupt control register 1 (57) Interrupt control register 2 (58) Processor status register (59) Program counter
002216 002316 002416 002516 002616 002716 002816 002916
FF16 FF16 FF16 0116 FF16 0016 0016 0016
002A16 0 0 0 0 ! ! ! 0 002B16 002C16 002D16 002E16 002F16 003016 003316 003416 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 2016 0016 1016 0116 0016 0016 0016 0816 0016 0016 0016 0016 0016 4816 0016 0016 0016 0016
(10) Port P4 direction register (11) Port P5 (12) Port P5 direction register (13) Port P6 (14) Port P6 direction register (15) Port P7 (16) Port P7 direction register (17) Port P8 (18) Port P8 direction register (19) Port P9 (20) Serial I/O3 control register 1 (21) Serial I/O3 control register 2 (22) Serial I/O3 control register 3 (23) Serial I/O3 automatic transfer data pointer (24) Serial I/O1 status register (25) Serial I/O1 control register (26) UART control register (27) Serial I/O2 control register (28) Watchdog timer control register (29) Timer X (low-order) (30) Timer X (high-order)
001216 ! 0 0 0 0 0 0 0 001416 001516 001616 001716 001916 001A16 001B16 001D16 001E16 002016 002116 0016 0016 0016 0016 8016 0016 E016 0016 3F16 FF16 FF16
(PS) ! ! ! ! ! 1 ! ! (PCH) FFFD16 contents (PCL) FFFC16 contents
Notes: ! : Not fixed Notes: Since the initial values for other than above-mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 67 Internal status at reset
61
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 3874 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. When using the XCIN oscillation circuit, XCIN and XCOUT pins' pullup resistors need to be invarid.
can be realized by reducing the drivability between XCIN and XCOUT. At reset or during STP instruction execution this bit is set to "1" and a reduced drivability that has an easy oscillation start is set. The sub-clock XCIN-XCOUT oscillating circuit can no directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate.
Oscillation Control (1) Stop mode
When the STP instruction is executed, the internal clock stops at an "H" level, and XIN and XCIN oscillators stop. The value set to the timer 1 latch and the timer 2 latch is set to timer 1 and timer 2. Either XIN or XCIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except the timer 3 count source selection bit (b4) are cleared to "0". Set the interrupt enable bits of timer 1 and timer 2 to the disabled state ("0") before executing the STP instruction. Oscillator restarts at reset or when an external interrupt is received, but the internal clock is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. Timer 1 latch and timer 2 latch should be set to proper values for stabilizing oscillation before executing the STP instruction.
Frequency Control (1) Middle-speed mode
The internal clock is the frequency of XIN divided by 8. After reset, this mode is selected.
(2) Double-speed mode
The internal clock is the frequency of XIN.
(3) High-speed mode
The internal clock is half the frequency of XIN.
(4) Low-speed mode
The internal clock is half the frequency of XCIN.
(2) Wait mode
If the WIT instruction is executed, the internal clock stops at an "H" level. The states of XIN and XCIN are the same as the state before executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted.
s Note
When switching the mode between double/middle/high-speed and low-speed, stabilize both XIN and XCIN oscillations. Sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode between double/middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3f(XCIN). It takes the cycle number mentioned below to switch between each mode (machine cycle = cycle of internal clock ). Double-speed modeExcept double-speed mode 1 to 8 machine cycles High-speed modeExcept high-speed mode 1 to 4 machine cycles Middle-speed modeExcept middle-speed mode 1 machine cycle Low-speed modeExcept low-speed mode 1 to 4 machine cycles The 3874 group operates in the previous mode while the mode is switched.
XCIN Rf
XCOUT Rd CCOUT
XIN
XOUT
CCIN
CIN
COUT
Fig. 68 Ceramic resonator circuit
(5) Low power dissipation mode
The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to "1". When the main clock XIN is restarted (by setting the main clock stop bit to "0"), set sufficient time for oscillation to stabilize. By clearing furthermore the XCOUT drivability selection bit (b3) of the CPU mode register to "0", low power consumption operation
XCIN Rf
XCOUT
XIN
XOUT Open
Rd
CCIN
External oscillation CCOUT circuit VCC VSS
Fig. 69 External clock input circuit
62
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCIN
XCOUT
"1"
"0" Port XC switch bit 1/16
XIN
XOUT
Main clock division ratio selection bits (Note) "10" 1/2 1/4 1/2
Timer 1 count source selection bit "1" Timer 1 "0" "0"
Timer 2 count source selection bit Timer 2 "1"
"00,01,11"
Main clock stop bit "00,10"
Main clock division ratio selection bits (Note) "01" Timing (internal clock) "11"
Q
S
S
Q
Q
S
R
STP instruction
WIT instruction
R
R
STP instruction
Reset Interrupt disable flag I Interrupt request
Note: When low-speed mode is selected, set port XC switch bit (b4) to "1."
Fig. 70 System clock generating circuit block diagram
63
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
CM7
"0""1"
CM6
"0""1"
High-speed mode (=3.15 MHz) CM7=0 High-speed mode CM6=0 6.3 MHz selected CM5=0 (XIN oscillating) CM4=0 (32 kHz stopped) CM3=1 (XCOUT drivability High) Middle-speed mode (=788 kHz) CM7=0 Middle-speed mode CM6=1 6.3 MHz selected CM5=0 (XIN oscillating) CM4=0 (32 kHz stopped) CM3=1 (XCOUT drivability High) Double-speed mode (=6.3 MHz) CM7=1 Double-speed mode CM6=1 6.3 MHz selected CM5=0 (XIN oscillating) CM4=0 (32 kHz stopped) CM3=1 (XCOUT drivability High)
CM6
CM7
"0""1"
"0""1"
CM4
"0
" CM 6 " CM "1 4 " "1 "
"1""0"
"1""0"
"0 C " M 0 "1 C " M4 "1 " "0 "
"0 C " M 7 "1 "
CM4
C
M
4
"1
"
"
0"
"0
High-speed mode (=3.15 MHz) CM7=0 High-speed mode CM6=0 6.3 MHz selected CM5=0 (XIN oscillating) CM4=1 (32 kHz oscillating) CM3=1 (XCOUT drivability High)
CM6
"0""1"
Middle-speed mode (=788 kHz) CM7=0 Middle-speed mode CM6=1 6.3 MHz selected CM5=0 (XIN oscillating) CM4=1 (32 kHz oscillating) CM3=1 (XCOUT drivability High)
CM7
"0""1"
CM7
Double-speed mode (=6.3 MHz) CM7=1 Double-speed mode CM6=1 6.3 MHz selected CM5=0 (XIN oscillating) CM4=1 (32 kHz oscillating) CM3=1 (XCOUT drivability High)
"0""1"
CM6
"0""1" "1""0" "0""1"
" CM "0 C 7 " M " "0 C 6 0" " M "1 3 " "1 "
"1""0"
"0""1"
CM7
CM3
CM7
CM6
Low-speed mode ( =16 kHz) CM7=1 Low-speed mode CM6=0 32 kHz selected CM5=0 (XIN oscillating) CM4=1 (32 kHz oscillating) CM3=0 (XCOUT drivability Low)
"0""1"
CM3
Low-speed mode (=16 kHz) CM7=1 Low-speed mode CM6=0 32 kHz selected CM5=0 (XIN oscillating) CM4=1 (32 kHz oscillating) CM3=1 (XCOUT drivability High)
b7
"0 CM " 6 "1 "
"1
b0 CPU mode register (CPUM: address 003B 16)
"0 C " M 3 " CM "1 5 " "0 "
Low-speed mode ( =16 kHz) CM7=1 Low consumption mode CM6=0 32 kHz selected CM5=1 (XIN stopped) CM4=1 (32 kHz oscillating) CM3=0 (XCOUT drivability Low)
CM3 : XCOUT drivability selection bit 0 : Low 1 : High CM4 : Port Xc switch bit 0 : I/O port function 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN- XOUT) stop bit 0 : Oscillating 1 : Stopped CM7,CM6 : Main clock division ratio selection bits CM7 CM6 0 0 : =f(XIN)/2 (high-speed mode) 0 1 : =f(XIN)/8 (middle-speed mode) 1 0 : =f(XCIN)/2 (low-speed mode) (double-speed mode) 1 1 : =f(XIN)
Notes 1: Switch the mode by the arrows shown between the mode blocks. (Do not switch between the modes directly without an arrow.) 2: All modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3: Timer operates in the wait mode. 4: When the stop mode is ended, wait time is generated automatically by connecting timer 1 and timer 2. 5: The example assumes that 6.3 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. indicates the internal clock. 6: We recommend that X COUT drivability selection bit is set to "1" (high) because reliance of oscillation stability is improved.
Fig. 71 State transitions of system clock
64
"1
CM4
"0
" CM 7 " CM "1 4 " "1 "
"0
"1""0"
"0
M1 C "
"
7
"
"0
CM
"
5
"1 "
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1". After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
Ports
The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction.
Serial I/O1 Interrupt Source Determination
* Use LDM, STA, etc., instructions to clear interrupt request bits assigned to the interrupt source determination register 1, the interrupt source determination register 2, the transmit status register, or the receive status register. (Do not use read-modifywrite instructions such as CLB, SEB, etc. Use the LDM or STA instruction to clear these bits.) * Request bits of interrupt source determination registers are not automatically cleared when an interrupt occurs. After an interrupt source has been determined, and before execution of the RTI or CLI instruction, the user must clear the bit by program. (Use the LDM or STA instruction to clear.) * The interrupt assigned to the interrupt source determination registers occur 1 instruction execution later than a normal interrupt. The maximum timing is 16 machine cycles in the MUL, DIV instructions. * In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to "1". Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. * In order to stop a transmit, set the transmit enable bit to "0" (transmit disable). Do not set only the serial I/O1 enable bit to "0". * A receive operation can be stopped by either setting the receive enable bit to "0" or the serial I/O1 enable bit to "0". * To stop a transmit when transferring in clock synchronous serial I/O mode, set both the transmit enable bit and the receive enable bit to "0" at the same time. * To set the serial I/O1 control register again, first set the transmit enable/receive enable bits to "0". Next, reset the transmit/receive circuits, and, finally, reset the serial I/O1 control register. * Note when confirming the transmit shift register completion flag and controlling the data transmit after writing a transmit data to the transmit buffer. There is a delay of 0.5 to 1.5 shift clock cycles while the transmit shift register completion flag goes from "1" to "0".
Decimal Calculations
* To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. * In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
* The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register.
65
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O3
* When writing "1" to the serial I/O initialization bit of the serial I/O3 control register 1, serial I/O3 is enabled, but each register is not initialized. Set the value of each register by program. * A serial I/O3 interrupt request occurs when "0" is written to the serial I/O initialization bit during an operation in automatic transfer serial I/O mode. Disable the interrupt enable bit as necessary by program.
A-D Converter/D-A Converter
* The A-D/D-A conversion register functions as an A-D conversion register during a read and a D-A conversion during a write. Accordingly, the D-A conversion register set value cannot be read out. * The comparator for A-D converter uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) is at least on 500 kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion.
* If switching the mode between low-speed and double-speed, switch the mode to middle/high-speed first, and then switch the mode to double-speed by program. Do not switch the mode from low-speed to double-speed directly. 1 to 4 machine cycles are required for switching from low-speed mode to other mode. Insert "clock switch timing wait" for switching the mode to middle/high-speed, and then switch the mode to double-speed. Table 8 lists the recommended transition process for system clock switch. Figure 72 shows the program example. Table 8 Clock switch combination Recommended transition process Low-speedHigh-speed Low-speedMiddle-speed Double-speedHigh-speed Double-speedMiddle-speed Double-speedLow-speed Middle-speedHigh-speed Middle-speedMiddle-speed Middle-speedLow-speed High-speedDouble-speed High-speedMIddle-speed High-speedLow-speed
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock is half of the XIN frequency.
Low-speed mode Middle/High-speed mode Double-speed mode switch LDM xx, CPUM ***Low-speed mode Middle/High-speed mode switch NOP Clock switch timing wait NOP (1 to 4 machine cycles are required for switching mode.) LDM yy, CPUM ***Switch mode to double-speed Note: CPUM = CPU mode register (address 003B16)
Data Link Layer Communication Control
* The data link layer communication control circuit stops after a reset. To restart or change modes, write "00XXXXX12" to the communication mode register. Note that bits 4 and 5 are readonly bits. * The P75/BUSOUT pin operates as a general-purpose pin after release from reset. As a general-purpose port, its input/output can be switched by the direction register.
Fig. 72 Program example
Clock Changes
* Use the LDM, STA, etc. instructions to modify the division ratio of internal system clock . (Do not use read-modify-write instructions such as CLB, SEB, etc.) * Do not modify the division ratio of the internal system clock until the mode has been changed. For details concerning the number of cycles necessary to change modes, refer to the clock section in the explanation of about function blocks. * Use the LDM, STA, etc., instructions to clear interrupt request bits assigned to the interrupt source determination register 1, the interrupt source determination register 2, the transmit status register, or the receive status register. (Do not use read-modifywrite instructions such as CLB, SEB, etc.) * Before executing the CLI or RTI instruction during an interrupt processing routine, use the LDM or STA instruction to clear the interrupt request bits of interrupt source determination registers which have completed the interrupt processing.
66
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: 1.Mask ROM Order Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies)
ROM PROGRAMMING METHOD
The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 73 is recommended to verify programming.
DATA R E QU I R E D F O R RO M W R I T I N G ORDERS
The following are necessary when ordering a ROM writing: 1.ROM Writing Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies)
Programming with PROM programmer
Screening (Caution) (150 C for 40 hours)
Verification with PROM programmer
Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours.
Fig. 73 Programming and testing of One Time PROM version
67
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Table 9 Absolute maximum ratings (extended operating temperature version and automotive version) Symbol VCC Parameter Power source voltage Input voltage P00-P07, P10-P17, P20-P27, P40-P47, P50-P57, P60-P67, P80-P87, VREF Input voltage RESET, XIN Input voltage P97 Output voltage P00-P07, P10-P17, P20-P27, P40-P47, P50-P57, P60-P67, P80-P87, XOUT Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3 to 7.0 Unit V
VI VI VI
P30-P37, P70-P77, All voltages are based on Vss. Output transistors are cut off. P30-P37, P70-P77, Ta = 25C
-0.3 to Vcc +0.3
V
-0.3 to Vcc +0.3 -0.3 to Vcc +0.3 -0.3 to Vcc +0.3 500 -40 to 85 -60 to 150
V V V mW C C
VO Pd Topr Tstg
Table 10 Recommended operating conditions (extended operating temperature version and automotive version, Vcc = 3.0 to 5.5 V, Ta = -40 to 85C, unless otherwise noted) Symbol Parameter At operating data link layer communication control circuit Double-speed mode Power source High-speed mode voltage Middle-speed mode Low-speed mode Power source voltage Analog reference voltage (when A-D converter is used) Analog reference voltage (when D-A converter is used) Analog power source voltage Analog input voltage AN0 to AN7 "H" input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P97 "H" input voltage RESET, XIN "L" input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P97 "L" input voltage RESET "L" input voltage XIN Power source voltage Min. Typ. Max. 4.0 5.0 5.5 5.5 5.0 4.0 5.5 5.0 4.0 5.5 5.0 3.0 5.5 5.0 3.0 0 VCC 2.0 VCC 3.0 0 VCC AVSS 0.8VCC 0.8VCC 0 0 0 VCC VCC 0.2VCC 0.2VCC 0.16VCC Unit V V V V V V V V V V V V V V V
VCC
VSS VREF AVSS VIA VIH VIH VIL VIL VIL
68
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 11 Recommended operating conditions (1) (extended operating temperature version and automotive version, Vcc = 3.0 to 5.5 V, Ta = -40 to 85C, unless otherwise noted) Symbol IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) Parameter "H" total peak output current (Note 1) P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 "H" total peak output current P40-P47, P50-P57, P60-P67, P70-P77 "L" total peak output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 "L" total peak output current P40-P47, P50-P57, P60-P67, P70-P77 "H" total average output current (Note 1) P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 "H" total average output current P40-P47, P50-P57, P60-P67, P70-P77 "L" total average output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 "L" total average output current P40-P47, P50-P57, P60-P67, P70-P77 "H" peak output current (Note 2) P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 "L" peak output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 "H" average output current (Note 3) P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 "L" average output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 Timer X, timer Y input oscillation frequency (at duty cycle of 50%) Main clock input oscillation frequency (Note 4) Sub-clock input oscillation frequency (Notes 4, 5) Min. Limits Typ. Max. -80 -80 80 80 -40 -40 40 40 Unit mA mA mA mA mA mA mA mA
IOH(peak)
-10
mA
IOL(peak)
10
mA
IOH(avg)
-5.0
mA
IOL(avg) f(CNTR0) f(CNTR1) f(XIN) f(XCIN)
5.0
mA
2.5 6.4 50
MHz MHz kHz
32.768
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms. 4: Choose an external oscillator which ensures no warps in the oscillation waveform as well as sufficient amplitude for the main clock oscillation circuit. Use according to the manufacturer's recommended conditions.
Table 12 Recommended operating conditions (2) (when ROM/PROM size is 60 Kbytes) (Vcc = 3.0 to 5.5 V, Ta = -40 to 85C, unless otherwise noted) Symbol Main clock input oscillation frequency Parameter High-speed mode/Middle-speed mode Double-speed mode (4.0 VCC < 4.5V) Double-speed mode (4.5 VCC 5.5V) Min. Limits Typ. Max. 6.4 2.8VCC-6.2 6.4 Unit MHz MHz MHz
f(XIN)
Note 5: When using the microcomputer in the low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
69
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 13 Electrical characteristics (extended operating temperature version and automotive version, Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = -40 to 85C, unless otherwise noted) Symbol Parameter "H" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P80-P87 (Note) "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 Hysteresis INT0-INT5, ADT, CNTR0, CNTR1 Hysteresis RXD, SCLK1, SIN2, SCLK2, P20-P27 Hysteresis RESET VI = VCC Valid hysteresis only when these pins is used as the function Test conditions IOH = -10 mA VCC = 4.0-5.5 V IOH = -1 mA VCC = 3.0-5.5 V IOL = 10 mA VCC = 4.0-5.5 V IOL = 1.0 mA VCC = 3.0-5.5 V Limits Typ. Unit V V 2.0 1.0 0.5 0.5 0.5 5.0 V V V V V A A A A A A A A V
Min. VCC-2.0 VCC-1.0
Max.
VOH
VOL
VT+ -VT- VT+ -VT- VT+-VT- IIH
"H" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 "H" input current "H" input current "H" input current P97 RESET XIN
IIH IIH IIH IIL
VI = VCC VI = VCC VI = VCC
5.0 5.0 4.0
"L" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 "L" input current P97 "L" input current RESET "L" input current XIN RAM hold voltage
VI = VSS VI = VSS VI = VSS VI = VSS When clock stopped 2.0
-5.0 -5.0 -5.0 -4.0 5.5
IIL IIL IIL VRAM
Note: When P45/TxD, P71/SOUT2, and P72/SCLK2 are CMOS output states (when not P-channel output disable states)
70
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 14 Electrical characteristics (extended operating temperature version and automotive version, Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = -40 to 85C, unless otherwise noted) Symbol Parameter Test conditions Double-speed mode, at operating data link layer communication control circuit f(XIN) = 6.29 MHz f(XCIN) = 32 kHz Output transistors "off" During A-D conversion Double-speed mode, at stopping data link layer communication control circuit f(XIN) = 6.29 MHz f(XCIN) = 32 kHz Output transistors "off" During A-D conversion Double-speed mode, at stopping data link layer communication control circuit f(XIN) = 6.29 MHz (in WIT state) f(XCIN) = 32 kHz Output transistors "off" During A-D conversion High-speed mode, at operating data link layer communication control circuit f(XIN) = 6.29 MHz f(XCIN) = 32 kHz Output transistors "off" During A-D conversion High-speed mode, at stopping data link layer communication control circuit f(XIN) = 6.29 MHz f(XCIN) = 32 kHz Output transistors "off" During A-D conversion High-speed mode, at stopping data link layer communication control circuit f(XIN) = 6.29 MHz (in WIT state) f(XCIN) = 32 kHz Output transistors "off" During A-D conversion Low-speed mode (VCC = 3.0 V) f(XIN) = stopped f(XCIN) = 32 kHz Low power dissipation mode (CM 5 = 0) Output transistors "off" Low-speed mode (VCC = 3.0 V) f(XIN) = stopped f(XCIN) = 32 kHz (in WIT state) Low power dissipation mode (CM5 = 0) Output transistors "off" Ta = 25C All oscillation stopped (Note) (in STP state) Ta = 85C Output transistors "off" (Note) Limits Typ. Unit
Min.
Max.
18.0
24.0
mA
12.0
18.0
mA
2.0
3.5
mA
12.0
19.0
mA
ICC
Power source current
8.0
12.0
mA
2.0
3.5
mA
60
200
A
20
40
A A A
0.1
1.0 10
Note: The A-D conversion is inactive. (The A-D conversion complete.) VREF current is not included.
71
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 15 A-D converter characteristics (extended operating temperature version and automotive version, VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = -40 to 85C, unless otherwise noted) Symbol - - tCONV RLADDER IVREF II(AD) Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current Analog port input current Test conditions Min. Limits Typ. 1 12 50 35 150 0.5 Max. 8 2.5 50 100 200 5.0 Unit Bits LSB tc() k A A
VREF = 5.0 V
Table 16 D-A converter characteristics (extended operating temperature version and automotive version, VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = -40 to 85C, unless otherwise noted) Symbol - - tsu RO IVREF Parameter Resolution Absolute accuracy Setting time Output resistor Reference power source input current Test conditions Min. Limits Typ. Max. 8 1.0 3.0 4.0 3.2 Unit Bits % s k mA
1
2.5
72
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS
Table 17 Timing requirements (extended operating temperature version and automotive version, VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWH(INT) tWL(CNTR) tWL(INT) tC(SCLK1) tC(SCLK2) tC(SCLK3) tWH(SCLK1) tWH(SCLK2) tWH(SCLK3) tWL(SCLK1) tWL(SCLK2) tWL(SCLK3) tsu(RxD-SCLK1) tsu(SIN2-SCLK2) tsu(RIN3-SCLK3) th(SCLK1-RxD) th(SCLK2-SIN2) th(SCLK3-SIN3) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width INT0 to INT5 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT5 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O3 clock input cycle time Serial I/O1 clock input "H" pulse width (Note) Serial I/O2 clock input "H" pulse width Serial I/O3 clock input "H" pulse width Serial I/O1 clock input "L" pulse width (Note) Serial I/O2 clock input "L" pulse width Serial I/O3 clock input "L" pulse width Serial I/O1 input setup time Serial I/O2 input setup time Serial I/O3 input setup time Serial I/O1 input hold time Serial I/O2 input hold time Serial I/O3 input hold time Limits Typ. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min. 2 159 63 63 200 80 80 80 80 800 1000 1000 370 400 400 370 400 400 220 200 200 100 200 200
Max.
Note : When bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16 is "0" (UART).
73
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 18 Switching characteristics (extended operating temperature version and automotive version, VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85C, unless otherwise noted) Symbol tWH (SCLK1) tWH (SCLK2) tWH (SCLK3) tWL (SCLK1) tWL (SCLK2) tWL (SCLK3) td (SCLK1-TXD) td (SCLK2-SOUT2) td (SCLK3-SOUT3) tV (SCLK1-TXD) tV (SCLK2-SOUT2) tV (SCLK3-SOUT3) tr (SCLK1) tf (SCLK1) tr (SCLK2) tf (SCLK2) tr (SCLK3) tf (SCLK3) tr (CMOS) tf (CMOS)
Notes 1: 2: 3: 4: 5: 6:
Parameter Serial I/O1 clock output "H" pulse width Serial I/O2 clock output "H" pulse width (Note 1) Serial I/O3 clock output "H" pulse width (Note 5) Serial I/O1 clock output "L" pulse width Serial I/O2 clock output "L" pulse width (Note 1) Serial I/O3 clock output "L" pulse width (Note 5) Serial I/O1 output delay time (Note 3) Serial I/O2 output delay time (Notes 1, 2) Serial I/O3 output delay time (Notes 5, 6) Serial I/O1 output valid time (Note 3) Serial I/O2 output valid time (Notes 1, 2) Serial I/O3 output valid time (Notes 5, 6) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output rising time (Note 1) Serial I/O2 clock output falling time (Note 1) Serial I/O3 clock output rising time (Note 5) Serial I/O3 clock output falling time (Note 5) CMOS output rising time (Note 4) CMOS output falling time (Note 4)
Limits Min. Typ. tC(SCLK1)/2-30 tC(SCLK2)/2-30 tC(SCLK3)/2-30 tC(SCLK1)/2-30 tC(SCLK2)/2-30 tC(SCLK3)/2-30
Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
140 140 140 -30 0 0 10 10 10 10 10 10 10 10 30 30 30 30 30 30 30 30
When P72/SCLK2 is CMOS output. When P71/SOUT2 is CMOS output. When P45/TXD is CMOS output. The XOUT pin is excluded. When P84/SCLK3 is CMOS output. When P82/SOUT3 is CMOS output.
74
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Measurement output pin 100 pF
CMOS output
Fig. 74 Circuit for measuring output switching characteristics
75
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing diagram
tC(CNTR) tWH(CNTR)
0.8VCC 0.2VCC
tWL(CNTR)
tWH(INT)
0.8VCC 0.2VCC
tWL(INT)
tW(RESET)
RESET 0.2VCC 0.8VCC
tC(XIN) tWH(XIN)
XIN 0.8VCC 0.16VCC
tWL(XIN)
SCLK1 SCLK2 SCLK3
tC(SCLK1), tC(SCLK2), tC(SCLK3) tf tWL(SCLK1), tWL(SCLK2), tWL(SCLK3) tr tWH(SCLK1), tWH(SCLK2), tWH(SCLK3)
0.8VCC 0.2VCC
tsu(RXD-SCLK1), tsu(SIN2-SCLK2), tsu(SIN3-SCLK3)
RXD SIN2 SIN3 0.8VCC 0.2VCC
th(SCLK1-RXD), th(SCLK2-SIN2), th(SCLK3-SIN3)
td(SCLK1-TXD),td(SCLK2-SOUT2),td(SCLK3-SOUT3)
TXD SOUT2 SOUT3
tv(SCLK1-TXD), tv(SCLK2-SOUT2), tv(SCLK3-SOUT3)
Fig. 75 Timing diagram (in single-chip mode)
76
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-76B<84A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38747M4T-XXXGP MITSUBISHI ELECTRIC
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
)
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM Sub ROM number of data link layer communication control circuit EPROM type (indicate the type used) (hexadecimal notation)
27512
EPROM address 000016 000F16 001016 001F16 002016 C07F16 C08016 FFFD16 FFFE16 FFFF16
Product name ASCII code : `M38747M4T-' Sub ROM number ASCII code
27101
EPROM address 000016 000F16 001016 001F16 002016 C07F16 C08016 FFFD16 FFFE16 1FFFF16
Product name ASCII code : `M38747M4T-' Sub ROM number ASCII code
Data ROM 16K-130 bytes
Data ROM 16K-130 bytes
In the address space of the microcomputer, the internal ROM area is from address C08016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. (1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38747M4T-" must be entered in addresses 000016 to 000916. And set the data "FF16" in addresses 000A16 to 000F16. ASCII codes and addresses are listed to the next page. (3) Addresses 001016 to 001F16 are ASCII codes reserved area of Sub ROM number for the data link layer communication control circuit. Write ASCII codes of Sub ROM number for the data link layer communication control circuit, which has been used at developing the submitted ROM, to addresses 001016 to 001F16 of EPROM certainly. Refer to ASCII codes of the next page at writing. (1/3)
77
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-76B<84A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38747M4T-XXXGP MITSUBISHI ELECTRIC
Address 000016 000116 000216 000316 000416 000516 000616 000716 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ASCII codes ` 0 ' =3016 ` 8 ' =3816 ` 1 ' =3116 ` 9 ' =3916 ` 2 ' =3216 ` A ' =4116 ` 3 ' =3316 ` B ' =4216 ` 4 ' =3416 ` C ' =4316 ` 5 ' =3516 ` D ' =4416 ` 6 ' =3616 ` E ' =4516 ` 7 ' =3716 ` F ' =4616 ` G ' =3816 ` H ' =3916 ` K ' =4B16 ` L ' =4C16 ` M' =4D16 ` N ' =4E16 ` P ' =5016 ` Q ' =5116 ` R ' =5216 ` Z ' =5A16 ` S ' =5316 ` T ' =5416 ` U ' =5516 ` V ' =5616 ` W '=5716 ` X ' =5816 ` Y ' =5916
`M' = 4D16 `3' = 3316 `8' = 3816 `7' = 3716 `4' = 3416 `7' = 3716 `M' = 4D16 `4' = 3416
` T ' =5416 ` - ' =2D16 FF16 FF16 FF16 FF16 FF16 FF16
We recommend the use of the following pseudo-command to set the start address of the assembier source program because ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM. ASCII codes of sub ROM number are written to addresses 001016 to 001716 by using the pseudo-command in the same way. EPROM type The pseudo-command 27512 *=$0000 .BYTE`M38747M4T-' 27101 *=$0000 .BYTE`M38747M4T-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (80P6S) and attach it to the mask ROM confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator Quartz crystal External clock input At what frequency? (2) How will you use the XCIN-XCOUT oscillator? Ceramic resonator External clock input Not use (Use for P40,P41) At what frequency? f(XcIN) = MHz Other ( f(XIN) = ) MHz
Quartz crystal Other ( )
(3) Which clock division ratio will you use? (possible to select plural)
= XIN (Double-speed mode) = XIN /8 (Middle-speed mode)
= XIN /2 (High-speed mode) = XcIN /2 (Low-speed mode)
(2/3)
78
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-76B<84A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38747M4T-XXXGP MITSUBISHI ELECTRIC
(4) Will you use the data link layer communication control circuit? Yes No g 4. Comments
(3/3)
79
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-77B<84A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38747M6T-XXXGP MITSUBISHI ELECTRIC
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
)
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM Sub ROM number of data link layer communication control circuit EPROM type (indicate the type used) (hexadecimal notation)
27512
EPROM address 000016 000F16 001016 001F16 002016 A07F16 A08016 FFFD16 FFFE16 FFFF16
Product name ASCII code : `M38747M6T-' Sub ROM number ASCII code
27101
EPROM address 000016 000F16 001016 001F16 002016 A07F16 A08016 FFFD16 FFFE16 1FFFF16
Product name ASCII code : `M38747M6T-' Sub ROM number ASCII code
Data ROM 24K-130 bytes
Data ROM 24K-130 bytes
In the address space of the microcomputer, the internal ROM area is from address A08016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. (1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38747M6T-" must be entered in addresses 000016 to 000916. And set the data "FF16" in addresses 000A16 to 000F16. ASCII codes and addresses are listed to the next page. (3) Addresses 001016 to 001F16 are ASCII codes reserved area of Sub ROM number for the data link layer communication control circuit. Write ASCII codes of Sub ROM number for the data link layer communication control circuit, which has been used at developing the submitted ROM, to addresses 001016 to 001F16 of EPROM certainly. Refer to ASCII codes of the next page at writing. (1/3)
80
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-77B<84A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38747M6T-XXXGP MITSUBISHI ELECTRIC
Address 000016 000116 000216 000316 000416 000516 000616 000716 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ASCII codes ` 0 ' =3016 ` 8 ' =3816 ` 1 ' =3116 ` 9 ' =3916 ` 2 ' =3216 ` A ' =4116 ` 3 ' =3316 ` B ' =4216 ` 4 ' =3416 ` C ' =4316 ` 5 ' =3516 ` D ' =4416 ` 6 ' =3616 ` E ' =4516 ` 7 ' =3716 ` F ' =4616 ` G ' =3816 ` H ' =3916 ` K ' =4B16 ` L ' =4C16 ` M' =4D16 ` N ' =4E16 ` P ' =5016 ` Q ' =5116 ` R ' =5216 ` Z ' =5A16 ` S ' =5316 ` T ' =5416 ` U ' =5516 ` V ' =5616 ` W '=5716 ` X ' =5816 ` Y ' =5916
`M' = 4D16 `3' = 3316 `8' = 3816 `7' = 3716 `4' = 3416 `7' = 3716 `M' = 4D16 `6' = 3616
` T ' =5416 ` - ' =2D16 FF16 FF16 FF16 FF16 FF16 FF16
We recommend the use of the following pseudo-command to set the start address of the assembier source program because ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM. ASCII codes of sub ROM number are written to addresses 001016 to 001716 by using the pseudo-command in the same way. EPROM type The pseudo-command 27512 *=$0000 .BYTE`M38747M6T-' 27101 *=$0000 .BYTE`M38747M6T-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (80P6S) and attach it to the mask ROM confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator Quartz crystal External clock input At what frequency? (2) How will you use the XCIN-XCOUT oscillator? Ceramic resonator External clock input Not use (Use for P40,P41) At what frequency? f(XcIN) = MHz Other ( f(XIN) = ) MHz
Quartz crystal Other ( )
(3) Which clock division ratio will you use? (possible to select plural)
= XIN (Double-speed mode) = XIN /8 (Middle-speed mode)
= XIN /2 (High-speed mode) = XcIN /2 (Low-speed mode)
(2/3)
81
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-77B<84A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38747M6T-XXXGP MITSUBISHI ELECTRIC
(4) Will you use the data link layer communication control circuit? Yes No g 4. Comments
(3/3)
82
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-75B<84A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38747MCT-XXXGP MITSUBISHI ELECTRIC
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
)
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM Sub ROM number of data link layer communication control circuit EPROM type (indicate the type used) (hexadecimal notation)
27512
EPROM address 000016 000F16 001016 001F16 002016 407F16 408016 FFFD16 FFFE16 FFFF16
Product name ASCII code : `M38747MCT-' Sub ROM number ASCII code
27101
EPROM address 000016 000F16 001016 001F16 002016 407F16 408016 FFFD16 FFFE16 1FFFF16
Product name ASCII code : `M38747MCT-' Sub ROM number ASCII code
Data ROM 48K-130 bytes
Data ROM 48K-130 bytes
In the address space of the microcomputer, the internal ROM area is from address 408016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. (1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38747MCT-" must be entered in addresses 000016 to 000916. And set the data "FF16" in addresses 000A16 to 000F16. ASCII codes and addresses are listed to the next page. (3) Addresses 001016 to 001F16 are ASCII codes reserved area of Sub ROM number for the data link layer communication control circuit. Write ASCII codes of Sub ROM number for the data link layer communication control circuit, which has been used at developing the submitted ROM, to addresses 001016 to 001F16 of EPROM certainly. Refer to ASCII codes of the next page at writing. (1/3)
83
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-75B<84A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38747MCT-XXXGP MITSUBISHI ELECTRIC
Address 000016 000116 000216 000316 000416 000516 000616 000716 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ASCII codes ` 0 ' =3016 ` 8 ' =3816 ` 1 ' =3116 ` 9 ' =3916 ` 2 ' =3216 ` A ' =4116 ` 3 ' =3316 ` B ' =4216 ` 4 ' =3416 ` C ' =4316 ` 5 ' =3516 ` D ' =4416 ` 6 ' =3616 ` E ' =4516 ` 7 ' =3716 ` F ' =4616 ` G ' =3816 ` H ' =3916 ` K ' =4B16 ` L ' =4C16 ` M' =4D16 ` N ' =4E16 ` P ' =5016 ` Q ' =5116 ` R ' =5216 ` Z ' =5A16 ` S ' =5316 ` T ' =5416 ` U ' =5516 ` V ' =5616 ` W '=5716 ` X ' =5816 ` Y ' =5916
`M' = 4D16 `3' = 3316 `8' = 3816 `7' = 3716 `4' = 3416 `7' = 3716 `M' = 4D16 `C' = 4316
` T ' =5416 ` - ' =2D16 FF16 FF16 FF16 FF16 FF16 FF16
We recommend the use of the following pseudo-command to set the start address of the assembier source program because ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM. ASCII codes of sub ROM number are written to addresses 001016 to 001716 by using the pseudo-command in the same way. EPROM type The pseudo-command 27512 *=$0000 .BYTE`M38747MCT-' 27101 *=$0000 .BYTE`M38747MCT-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (80P6S) and attach it to the mask ROM confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator Quartz crystal External clock input At what frequency? (2) How will you use the XCIN-XCOUT oscillator? Ceramic resonator External clock input Not use (Use for P40,P41) At what frequency? f(XcIN) = MHz Other ( f(XIN) = ) MHz
Quartz crystal Other ( )
(3) Which clock division ratio will you use? (possible to select plural)
= XIN (Double-speed mode) = XIN /8 (Middle-speed mode)
= XIN /2 (High-speed mode) = XcIN /2 (Low-speed mode)
(2/3)
84
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-75B<84A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38747MCT-XXXGP MITSUBISHI ELECTRIC
(4) Will you use the data link layer communication control circuit? Yes No g 4. Comments
(3/3)
85
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-78B<84A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38749EFT-XXXGP MITSUBISHI ELECTRIC
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
)
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM programming data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM Sub ROM number of data link layer communication control circuit EPROM type (indicate the type used) (hexadecimal notation)
27512
EPROM address 000016 000F16 001016 001F16 002016 107F16 108016 FFFD16 FFFE16 FFFF16
Product name ASCII code : `M38749EFT-' Sub ROM number ASCII code
27101
EPROM address 000016 000F16 001016 001F16 002016 107F16 108016 FFFD16 FFFE16 1FFFF16
Product name ASCII code : `M38749EFT-' Sub ROM number ASCII code
Data ROM 60K-130 bytes
Data ROM 60K-130 bytes
In the address space of the microcomputer, the internal ROM area is from address 108016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. (1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38749EFT-" must be entered in addresses 000016 to 000916. And set the data "FF16" in addresses 000A16 to 000F16. The ASCII codes and addresses are listed to the next page. (3) Addresses 001016 to 001F16 are ASCII codes reserved area of Sub ROM number for the data link layer communication control circuit. Write ASCII codes of Sub ROM number for the data link layer communication control circuit, which has been used at developing the submitted ROM, to addresses 001016 to 001F16 of EPROM certainly. Refer to ASCII codes of the next page at writing. (1/3)
86
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-78B<84A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38749EFT-XXXGP MITSUBISHI ELECTRIC
Address 000016 000116 000216 000316 000416 000516 000616 000716 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ASCII codes ` 0 ' =3016 ` 8 ' =3816 ` 1 ' =3116 ` 9 ' =3916 ` 2 ' =3216 ` A ' =4116 ` 3 ' =3316 ` B ' =4216 ` 4 ' =3416 ` C ' =4316 ` 5 ' =3516 ` D ' =4416 ` 6 ' =3616 ` E ' =4516 ` 7 ' =3716 ` F ' =4616 ` G ' =3816 ` H ' =3916 ` K ' =4B16 ` L ' =4C16 ` M' =4D16 ` N ' =4E16 ` P ' =5016 ` Q ' =5116 ` R ' =5216 ` Z ' =5A16 ` S ' =5316 ` T ' =5416 ` U ' =5516 ` V ' =5616 ` W '=5716 ` X ' =5816 ` Y ' =5916
`M' = 4D16 `3' = 3316 `8' = 3816 `7' = 3716 `4' = 3416 `9' = 3916 `E' = 4516 `F' = 4616
` T ' =5416 ` - ' =2D16 FF16 FF16 FF16 FF16 FF16 FF16
We recommend the use of the following pseudo-command to set the start address of the assembier source program because ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM. ASCII codes of sub ROM number are written to addresses 001016 to 001716 by using the pseudo-command in the same way. EPROM type The pseudo-command 27512 *=$0000 .BYTE`M38749EFT-' 27101 *=$0000 .BYTE`M38749EFT-'
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (80P6S) and attach it to the ROM programming confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator Quartz crystal External clock input At what frequency? (2) How will you use the XCIN-XCOUT oscillator? Ceramic resonator External clock input Not use (Use for P40,P41) At what frequency? f(XcIN) = MHz Quartz crystal Other ( ) Other ( f(XIN) = ) MHz
(3) Which clock division ratio will you use? (possible to select plural)
= XIN (Double-speed mode) = XIN /8 (Middle-speed mode)
= XIN /2 (High-speed mode) = XcIN /2 (Low-speed mode)
(2/3)
87
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-78B<84A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38749EFT-XXXGP MITSUBISHI ELECTRIC
(4) Will you use the data link layer communication control circuit? Yes No g 4. Comments
(3/3)
88
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
80P6S (80-PIN QFP) MARK SPECIFICATION FORM 80P6D, 80P6Q (80-PIN Fine-pitch QFP)
Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark
60 41
61
40
Mitsubishi IC catalog name Mitsubishi IC catalog name
Mitsubishi product number (6-digit, or 7-digit)
80
21
1
20
B. Customer's Parts Number + Mitsubishi IC Catalog Name
60 41
61
40
80
21
1
20
Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Notes 1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's parts number can be up to 10 alphanumeric characters for capital letters, hyphens, commas, periods and so on. 4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required
C. Special Mark Required
60 41
5 : The allocation of Mitsubishi IC catalog name and Mitsubishi product number is different on the package owing to the number of Mitsubishi IC catalog name's characters, and the requiring Mitsubishi logo or not. Notes 1 : If Special mark is to be printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated technically as close as possible. Mitsubishi product number (6-digit, or 7-digit) and Mask ROM number (3-digit) are always marked for sorting the products. 2 : If special character fonts (e.g., customer's trade mark logo) must be used in Special Mark, check the box below. For the new special character fonts, a clean font original (ideally logo drawing) must be submitted. Special character fonts required
61
40
80
21
1
20
89
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
80P6S-A
EIAJ Package Code QFP80-P-1414-0.65 HD D JEDEC Code Weight(g) 1.11 Lead Material Alloy 42
Plastic 80pin 14!14mm body QFP
MD
e
1
60
b2
80
61
I2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME Dimension in Millimeters Min Nom Max - - 3.05 0.1 0.2 0 2.8 - - 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 13.8 14.0 14.2 0.65 - - 16.5 16.8 17.1 16.5 16.8 17.1 0.4 0.6 0.8 1.4 - - 0.1 - - 0 10 - 0.35 - - - - 1.3 - - 14.6 - - 14.6
20
41
HE
E
21
40
A L1
F e y b
A2
A1
L Detail F
80D0
EIAJ Package Code - JEDEC Code - Weight(g)
c
Glass seal 80pin QFN
21.00.2
3.32MAX 1.78TYP
41 40
18.40.15 0.8TYP 0.6TYP
64 65
0.8TYP
ME 1.2TYP
25 80 24 1
INDEX
0.5TYP
1.2TYP
90
0.8TYP 12.00.15
15.60.2
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
*
* *
*
(c) 1998 MITSUBISHI ELECTRIC CORP. New publication, effective Jun. 1998. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.0 First Edition
3874 GROUP DATA SHEET
Revision Description Rev. date 980602
(1/1)

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